riscv/rocket-chip
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WIP scala compile and firrtl elaborate; monitor error

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This commit is contained in:
Henry Cook
2016-11-11 13:07:45 -08:00
parent afa1a6d549
commit 71315d5cf5
10 changed files with 136 additions and 158 deletions
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29
src/main/scala/rocket/dcache.scala
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@ -42,7 +42,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends LazyModule with HasL1HellaCacheParameters {
val node = TLClientNode(TLClientParameters(supportsProbe = TransferSizes(cacheBlockBytes)))
val node = TLClientNode(TLClientParameters(
sourceId = IdRange(0, maxUncachedInFlight),
supportsProbe = TransferSizes(cacheBlockBytes)))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@ -54,12 +56,31 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
val edge = node.edgesOut(0)
val tl_out = io.mem(0)
val grantackq = Module(new Queue(tl_out.e.bits,1))
/* TODO
edge.manager.managers.foreach { m =>
// If a slave supports read at all, it must support all TL Legacy requires
if (m.supportsGet) {
require (m.supportsGet.contains(TransferSizes(1, tlDataBytes)))
require (m.supportsGet.contains(TransferSizes(tlDataBeats * tlDataBytes)))
}
// Likewise, any put support must mean full put support
if (m.supportsPutPartial) {
require (m.supportsPutPartial.contains(TransferSizes(1, tlDataBytes)))
require (m.supportsPutPartial.contains(TransferSizes(tlDataBeats * tlDataBytes)))
}
// Any atomic support => must support 32-bit size
if (m.supportsArithmetic) { require (m.supportsArithmetic.contains(TransferSizes(4))) }
if (m.supportsLogical) { require (m.supportsLogical .contains(TransferSizes(4))) }
// We straight-up require Acquire support, this is a cache afterall?
require (edge.manager.anySupportsAcquire)
}
*/
require(rowBits == encRowBits) // no ECC
require(refillCyclesPerBeat == 1)
require(rowBits >= coreDataBits)
val grantackq = Module(new Queue(tl_out.e.bits,1))
// tags
val replacer = p(Replacer)()
def onReset = L1Metadata(UInt(0), ClientMetadata.onReset)
@ -132,7 +153,7 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
require(nWays == 1)
metaWriteArb.io.out.ready := true
metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
val inScratchpad = addrMap(s"TL2:dmem${tileId}").containsAddress(s1_paddr)
val inScratchpad = addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr)
val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
(inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
} else {

5
src/main/scala/rocket/nbdcache.scala
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@ -73,14 +73,14 @@ trait HasMissInfo extends HasL1HellaCacheParameters {
val way_en = Bits(width = nWays)
}
class HellaCacheReqInternal(implicit p: Parameters) extends L1HellaCacheBundle()(p)
class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp {
val phys = Bool()
}
class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class HellaCacheResp(implicit p: Parameters) extends L1HellaCacheBundle()(p)
class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp
with HasCoreData {
val replay = Bool()
@ -1245,6 +1245,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
object HellaCache {
def apply(cfg: DCacheConfig)(implicit p: Parameters) = LazyModule(new DCache)
// TODO convert non-blocking cache
// if (cfg.nMSHRs == 0) Module(new DCache()).io
// else Module(new HellaCache(cfg)).io
}

2
src/main/scala/rocket/rocket.scala
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@ -75,8 +75,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val nCustomMrwCsrs = p(NCustomMRWCSRs)
val nCores = p(NTiles)
val tileId = p(TileId)
// fetchWidth doubled, but coreInstBytes halved, for RVC
val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1)

30
src/main/scala/rocket/tile.scala
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@ -23,21 +23,35 @@ case class RoccParameters(
nPTWPorts : Int = 0,
useFPU: Boolean = false)
class RocketTile(implicit p: Parameters) extends LazyModule {
val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
val icacheParams = p.alterPartial({ case CacheName => "L1I" })
class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val dcacheParams = p.alterPartial({
case CacheName => "L1D"
case TLId => "L1toL2"
case TileId => tileId // TODO using this messes with Heirarchical P&R
})
val icacheParams = p.alterPartial({
case CacheName => "L1I"
case TLId => "L1toL2"
})
//TODO val intNode = IntInputNode()
val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val ucLegacy = LazyModule(new TLLegacy()(p))
val ucLegacy = LazyModule(new TLLegacy()(icacheParams))
val cachedOut = TLOutputNode()
val uncachedOut = TLOutputNode()
cachedOut := dcache.node
uncachedOut := ucLegacy.node
val masterNodes = List(cachedOut, uncachedOut)
(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val cached = dcache.node.bundleOut
val uncached = ucLegacy.node.bundleOut
val cached = cachedOut.bundleOut
val uncached = uncachedOut.bundleOut
val slave = slaveNode.map(_.bundleIn)
val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts().asInput
@ -49,7 +63,7 @@ class RocketTile(implicit p: Parameters) extends LazyModule {
val nRocc = buildRocc.size
val nFPUPorts = buildRocc.filter(_.useFPU).size
val core = Module(new Rocket)
val core = Module(new Rocket()(dcacheParams))
val icache = Module(new Frontend()(icacheParams))
val ptwPorts = ListBuffer(icache.io.ptw, dcache.module.io.ptw)
@ -108,7 +122,7 @@ class RocketTile(implicit p: Parameters) extends LazyModule {
uncachedArbPorts ++= roccs.flatMap(_.io.utl) // TODO no difference between io.autl and io.utl for now
}
val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size))
val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size)(icacheParams))
uncachedArb.io.in <> uncachedArbPorts
ucLegacy.module.io.legacy <> uncachedArb.io.out