riscv/rocket-chip
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Make RocketTileWrapper a BaseTile

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This commit is contained in:
Andrew Waterman
2017-10-05 22:46:16 -07:00
parent 4645b61fd3
commit 71205b70cc
2 changed files with 8 additions and 9 deletions
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15
src/main/scala/tile/RocketTile.scala
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@@ -181,7 +181,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
ptw.io.requestor <> ptwPorts
}
abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends LazyModule {
class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTileBundle(_outer)
with CanHaltAndCatchFire {
val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType)
}
abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends BaseTile(rtp) {
val rocket = LazyModule(new RocketTile(rtp))
val asyncIntNode : IntInwardNode
val periphIntNode : IntInwardNode
@@ -213,13 +218,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters)
def outputInterruptXingLatency: Int
lazy val module = new LazyModuleImp(this) {
val io = IO(new CoreBundle
with HasExternallyDrivenTileConstants
with CanHaveInstructionTracePort
with CanHaltAndCatchFire {
val halt_and_catch_fire = rocket.module.io.halt_and_catch_fire.map(_.cloneType)
})
override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
// signals that do not change based on crossing type:
rocket.module.io.hartid := io.hartid
rocket.module.io.reset_vector := io.reset_vector