From 71205b70cc56b9c07cea3d8d9ea5ebd50b01e9a6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 5 Oct 2017 22:46:16 -0700 Subject: [PATCH] Make RocketTileWrapper a BaseTile --- src/main/scala/coreplex/RocketCoreplex.scala | 2 +- src/main/scala/tile/RocketTile.scala | 15 +++++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index e7009316..43a3c4c1 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -36,7 +36,7 @@ trait HasRocketTiles extends HasSystemBus // Make a wrapper for each tile that will wire it to coreplex devices and crossbars, // according to the specified type of clock crossing. val wiringTuple = localIntNodes.zip(tileParams) - val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case (lip, tp) => + val rocket_tiles: Seq[BaseTile] = wiringTuple.map { case (lip, tp) => val pWithExtra = p.alterPartial { case TileKey => tp case BuildRoCC => tp.rocc diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 9d9b7b94..6fec665f 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -181,7 +181,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne ptw.io.requestor <> ptwPorts } -abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends LazyModule { +class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTileBundle(_outer) + with CanHaltAndCatchFire { + val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType) +} + +abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends BaseTile(rtp) { val rocket = LazyModule(new RocketTile(rtp)) val asyncIntNode : IntInwardNode val periphIntNode : IntInwardNode @@ -213,13 +218,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) def outputInterruptXingLatency: Int - lazy val module = new LazyModuleImp(this) { - val io = IO(new CoreBundle - with HasExternallyDrivenTileConstants - with CanHaveInstructionTracePort - with CanHaltAndCatchFire { - val halt_and_catch_fire = rocket.module.io.halt_and_catch_fire.map(_.cloneType) - }) + override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) { // signals that do not change based on crossing type: rocket.module.io.hartid := io.hartid rocket.module.io.reset_vector := io.reset_vector