riscv/rocket-chip
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Remove splitMetadata option from L1 caches

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This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
This commit is contained in:
Andrew Waterman 2017-03-30 15:43:38 -07:00
parent c61714a465
commit 70e7e90c02
3 changed files with 4 additions and 20 deletions
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21
src/main/scala/rocket/HellaCache.scala
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@ -20,7 +20,6 @@ case class DCacheParams(
nWays: Int = 4, nWays: Int = 4,
rowBits: Int = 64, rowBits: Int = 64,
nTLBEntries: Int = 32, nTLBEntries: Int = 32,
splitMetadata: Boolean = false,
ecc: Option[Code] = None, ecc: Option[Code] = None,
nMSHRs: Int = 1, nMSHRs: Int = 1,
nSDQ: Int = 17, nSDQ: Int = 17,
@ -246,23 +245,11 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters)
when (rst) { rst_cnt := rst_cnt+UInt(1) } when (rst) { rst_cnt := rst_cnt+UInt(1) }
val metabits = rstVal.getWidth val metabits = rstVal.getWidth
val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
if (hasSplitMetadata) { when (rst || io.write.valid) {
val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) } tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask)
val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
(0 until nWays).foreach { (i) =>
when (rst || (io.write.valid && wmask(i))) {
tag_arrs(i).write(waddr, wdata)
}
io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
}
} else {
val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
when (rst || io.write.valid) {
tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
}
io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
} }
io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
io.write.ready := !rst io.write.ready := !rst

1
src/main/scala/rocket/ICache.scala
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@ -18,7 +18,6 @@ case class ICacheParams(
rowBits: Int = 128, rowBits: Int = 128,
nTLBEntries: Int = 32, nTLBEntries: Int = 32,
cacheIdBits: Int = 0, cacheIdBits: Int = 0,
splitMetadata: Boolean = false,
ecc: Option[Code] = None, ecc: Option[Code] = None,
blockBytes: Int = 64) extends L1CacheParams { blockBytes: Int = 64) extends L1CacheParams {
def replacement = new RandomReplacement(nWays) def replacement = new RandomReplacement(nWays)

2
src/main/scala/tile/L1Cache.scala
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@ -15,7 +15,6 @@ trait L1CacheParams {
def nWays: Int def nWays: Int
def rowBits: Int def rowBits: Int
def nTLBEntries: Int def nTLBEntries: Int
def splitMetadata: Boolean
def ecc: Option[Code] def ecc: Option[Code]
def blockBytes: Int def blockBytes: Int
} }
@ -39,7 +38,6 @@ trait HasL1CacheParameters {
def rowOffBits = log2Up(rowBytes) def rowOffBits = log2Up(rowBytes)
def code = cacheParams.ecc.getOrElse(new IdentityCode) def code = cacheParams.ecc.getOrElse(new IdentityCode)
def nTLBEntries = cacheParams.nTLBEntries def nTLBEntries = cacheParams.nTLBEntries
def hasSplitMetadata = cacheParams.splitMetadata
def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits