From 70e7e90c02cf526adb7b13a8b3d4aa124cf58468 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 30 Mar 2017 15:43:38 -0700
Subject: [PATCH] Remove splitMetadata option from L1 caches

This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
---
 src/main/scala/rocket/HellaCache.scala | 21 ++++-----------------
 src/main/scala/rocket/ICache.scala     |  1 -
 src/main/scala/tile/L1Cache.scala      |  2 --
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala
index 2d4f1178..6a8bfe6b 100644
--- a/src/main/scala/rocket/HellaCache.scala
+++ b/src/main/scala/rocket/HellaCache.scala
@@ -20,7 +20,6 @@ case class DCacheParams(
     nWays: Int = 4,
     rowBits: Int = 64,
     nTLBEntries: Int = 32,
-    splitMetadata: Boolean = false,
     ecc: Option[Code] = None,
     nMSHRs: Int = 1,
     nSDQ: Int = 17,
@@ -246,23 +245,11 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters)
   when (rst) { rst_cnt := rst_cnt+UInt(1) }
 
   val metabits = rstVal.getWidth
-
-  if (hasSplitMetadata) {
-    val tag_arrs = List.fill(nWays){ SeqMem(nSets, UInt(width = metabits)) }
-    val tag_readout = Wire(Vec(nWays,rstVal.cloneType))
-    (0 until nWays).foreach { (i) =>
-      when (rst || (io.write.valid && wmask(i))) {
-        tag_arrs(i).write(waddr, wdata)
-      }
-      io.resp(i) := rstVal.fromBits(tag_arrs(i).read(io.read.bits.idx, io.read.valid && rmask(i)))
-    }
-  } else {
-    val tag_arr = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
-    when (rst || io.write.valid) {
-      tag_arr.write(waddr, Vec.fill(nWays)(wdata), wmask)
-    }
-    io.resp := tag_arr.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
+  val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
+  when (rst || io.write.valid) {
+    tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask)
   }
+  io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
 
   io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
   io.write.ready := !rst
diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala
index f87aad4a..2540c9e1 100644
--- a/src/main/scala/rocket/ICache.scala
+++ b/src/main/scala/rocket/ICache.scala
@@ -18,7 +18,6 @@ case class ICacheParams(
     rowBits: Int = 128,
     nTLBEntries: Int = 32,
     cacheIdBits: Int = 0,
-    splitMetadata: Boolean = false,
     ecc: Option[Code] = None,
     blockBytes: Int = 64) extends L1CacheParams {
   def replacement = new RandomReplacement(nWays)
diff --git a/src/main/scala/tile/L1Cache.scala b/src/main/scala/tile/L1Cache.scala
index 54e1cdee..21b31425 100644
--- a/src/main/scala/tile/L1Cache.scala
+++ b/src/main/scala/tile/L1Cache.scala
@@ -15,7 +15,6 @@ trait L1CacheParams {
   def nWays:         Int
   def rowBits:       Int
   def nTLBEntries:   Int
-  def splitMetadata: Boolean
   def ecc:           Option[Code]
   def blockBytes:    Int
 }
@@ -39,7 +38,6 @@ trait HasL1CacheParameters {
   def rowOffBits = log2Up(rowBytes)
   def code = cacheParams.ecc.getOrElse(new IdentityCode)
   def nTLBEntries = cacheParams.nTLBEntries
-  def hasSplitMetadata = cacheParams.splitMetadata
 
   def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
   def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits