Remove splitMetadata option from L1 caches
This is a property of the specific cache microarchitecture, not actually an independently tunable knob.
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@ -15,7 +15,6 @@ trait L1CacheParams {
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def nWays: Int
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def rowBits: Int
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def nTLBEntries: Int
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def splitMetadata: Boolean
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def ecc: Option[Code]
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def blockBytes: Int
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}
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@ -39,7 +38,6 @@ trait HasL1CacheParameters {
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def rowOffBits = log2Up(rowBytes)
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def code = cacheParams.ecc.getOrElse(new IdentityCode)
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def nTLBEntries = cacheParams.nTLBEntries
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def hasSplitMetadata = cacheParams.splitMetadata
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def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
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def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
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