riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

error out for PCWM-L, port width mismatch

Browse Source
This commit is contained in:
Yunsup Lee 2014-09-25 06:43:03 -07:00
parent 15fb4730ec
commit 70b0f9fd4d
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fsim/Makefrag
View File

@ -33,7 +33,7 @@ verilog: $(sim_vsrcs)
VCS = vcs -full64
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \

2
vsim/Makefrag
View File

@ -32,7 +32,7 @@ verilog: $(sim_vsrcs)
VCS = vcs -full64
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \