From 70b0f9fd4d6029dc65f6b936435a67484d89c792 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 25 Sep 2014 06:43:03 -0700 Subject: [PATCH] error out for PCWM-L, port width mismatch --- fsim/Makefrag | 2 +- vsim/Makefrag | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fsim/Makefrag b/fsim/Makefrag index caf1cabd..b3056b7b 100644 --- a/fsim/Makefrag +++ b/fsim/Makefrag @@ -33,7 +33,7 @@ verilog: $(sim_vsrcs) VCS = vcs -full64 -VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \ +VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ +rad +v2k +vcs+lic+wait \ +vc+list -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ diff --git a/vsim/Makefrag b/vsim/Makefrag index 79c9bafb..0db5787f 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -32,7 +32,7 @@ verilog: $(sim_vsrcs) VCS = vcs -full64 -VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \ +VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \ +rad +v2k +vcs+lic+wait \ +vc+list -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \