riscv/rocket-chip
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error out for PCWM-L, port width mismatch

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Yunsup Lee committed 2014-09-25 06:50:50 -07:00
1 parent 15fb4730ec
commit 70b0f9fd4d
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fsim/Makefrag
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@@ -33,7 +33,7 @@ verilog: $(sim_vsrcs)
VCS = vcs -full64
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \