riscv/rocket-chip
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Fix Chisel3 build for UseVM=false

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This commit is contained in:
Andrew Waterman
2016-03-30 22:48:31 -07:00
parent 8ad8e8a691
commit 70664bbca0
1 changed files with 6 additions and 6 deletions
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12
rocket/src/main/scala/tlb.scala
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@@ -83,15 +83,15 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val ptw = new TLBPTWIO
}
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
val state = Reg(init=s_ready)
val r_refill_tag = Reg(UInt())
val r_refill_waddr = Reg(UInt())
val r_req = Reg(new TLBReq)
val tag_cam = Module(new RocketCAM)
val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn)
val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(UInt(), 4)
val state = Reg(init=s_ready)
val r_refill_tag = Reg(tag_cam.io.write_tag)
val r_refill_waddr = Reg(tag_cam.io.write_addr)
val r_req = Reg(new TLBReq)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
tag_cam.io.tag := lookup_tag
tag_cam.io.write := state === s_wait && io.ptw.resp.valid