riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink: SRAM can emulate incompletely populated memory

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-07-07 21:08:14 -07:00
parent 9310a33e77
commit 702143eb33
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/tilelink/SRAM.scala
View File

@ -8,14 +8,14 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule
{
private val resources =
name.map(new SimpleDevice(_, Seq("sifive,sram0")).reg("mem")).getOrElse(new MemoryDevice().reg)
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
address = List(address) ++ errors,
resources = resources,
regionType = RegionType.UNCACHED,
executable = executable,