From 702143eb33234e4bc1278f71699c48a7803880e8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 7 Jul 2017 21:08:14 -0700 Subject: [PATCH] tilelink: SRAM can emulate incompletely populated memory --- src/main/scala/tilelink/SRAM.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index 38d2184e..774b337d 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -8,14 +8,14 @@ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ -class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule +class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule { private val resources = name.map(new SimpleDevice(_, Seq("sifive,sram0")).reg("mem")).getOrElse(new MemoryDevice().reg) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( - address = List(address), + address = List(address) ++ errors, resources = resources, regionType = RegionType.UNCACHED, executable = executable,