riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Chisel3 compatibility fix for <>

Browse Source
This commit is contained in:
Andrew Waterman
2015-08-05 15:33:10 -07:00
parent 34b9a7fdc5
commit 700910adff
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/Network.scala
View File

@@ -51,7 +51,7 @@ abstract class RocketChipNetwork(
case (m, i) => { case (m, i) => {
val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId)) val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
val q = Module(new TileLinkEnqueuer(managerDepths)) val q = Module(new TileLinkEnqueuer(managerDepths))
m <> p.io.manager p.io.manager <> m
p.io.network <> q.io.manager p.io.network <> q.io.manager
q.io.client q.io.client
} }