From 700910adff25205b2549732d12e8bfe81f8e98db Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 5 Aug 2015 15:33:10 -0700 Subject: [PATCH] Chisel3 compatibility fix for <> --- src/main/scala/Network.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/Network.scala b/src/main/scala/Network.scala index ccb69686..cfdf8364 100644 --- a/src/main/scala/Network.scala +++ b/src/main/scala/Network.scala @@ -51,7 +51,7 @@ abstract class RocketChipNetwork( case (m, i) => { val p = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId)) val q = Module(new TileLinkEnqueuer(managerDepths)) - m <> p.io.manager + p.io.manager <> m p.io.network <> q.io.manager q.io.client }