riscv/rocket-chip
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket

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This commit is contained in:
Huy Vo 2012-03-13 12:34:39 -07:00
commit 6e32cc8b20
1 changed files with 3 additions and 3 deletions
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6
uncore/coherence.scala
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@ -147,8 +147,8 @@ trait FourStateCoherence extends CoherencePolicy {
def isHit ( cmd: Bits, state: UFix): Bool = {
val (read, write) = cpuCmdToRW(cmd)
((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
(state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
}
//TODO: do we need isPresent() for determining that a line needs to be
@ -600,7 +600,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
conflicts(i) := t.busy && x_init.valid && coherenceConflict(t.addr, x_init.bits.address)
}
x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
want_to_abort_arr(j) := conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits))
want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits)))
x_abort.valid := Bool(false)
switch(abort_state_arr(j)) {