riscv/rocket-chip
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fix DTLB permissions bug

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This commit is contained in:
Andrew Waterman 2012-04-16 21:20:25 -07:00
parent 1ed89f1cab
commit 6d8fc74378
1 changed files with 8 additions and 5 deletions
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13
rocket/src/main/scala/dtlb.scala
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@ -139,15 +139,18 @@ class rocketDTLB(entries: Int) extends Component
} }
} }
val access_fault_common = val load_fault_common = tlb_hit &&
tlb_hit &&
((status_s && !sr_array(tag_hit_addr)) || ((status_s && !sr_array(tag_hit_addr)) ||
(status_u && !ur_array(tag_hit_addr)) || (status_u && !ur_array(tag_hit_addr)) ||
bad_va) bad_va)
val store_fault_common = tlb_hit &&
((status_s && !sw_array(tag_hit_addr)) ||
(status_u && !uw_array(tag_hit_addr)) ||
bad_va)
io.cpu_resp.xcpt_ld := access_fault_common && (req_load || req_amo) io.cpu_resp.xcpt_ld := load_fault_common && (req_load || req_amo)
io.cpu_resp.xcpt_st := access_fault_common && (req_store || req_amo) io.cpu_resp.xcpt_st := store_fault_common && (req_store || req_amo)
io.cpu_resp.xcpt_pf := access_fault_common && req_pf io.cpu_resp.xcpt_pf := load_fault_common && req_pf
io.cpu_req.ready := (state === s_ready) && !tlb_miss; io.cpu_req.ready := (state === s_ready) && !tlb_miss;
io.cpu_resp.miss := tlb_miss; io.cpu_resp.miss := tlb_miss;