riscv/rocket-chip
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Fixed emulator Makefile + extra info in the README file

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This commit is contained in:
Miquel Moreto 2012-10-16 11:06:48 -07:00
parent aa3dc422b4
commit 6d49dc51a0
2 changed files with 7 additions and 1 deletions
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6
README
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@ -26,6 +26,12 @@ BUILDING THE TOOLCHAIN:
cd riscv-asmtests-bmarks/riscv-bmarks/ cd riscv-asmtests-bmarks/riscv-bmarks/
make make
To build dramsim2 (tagged version 2.1):
cd dramsim2/
git checkout v2.1
make libdramsim.so
BUILDING THE PROJECT: BUILDING THE PROJECT:

2
emulator/Makefile
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@ -10,7 +10,7 @@ CXXSRCS := emulator disasm
CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc
DRAMSIM2_PATH := ../dramsim2/ DRAMSIM2_PATH := ../dramsim2/
CXXFLAGS := $(CXXFLAGS) -I$(DRAMSIM2_PATH) -L$(DRAMSIM2_PATH) -ldramsim CXXFLAGS := $(CXXFLAGS) -I$(DRAMSIM2_PATH) -L$(DRAMSIM2_PATH) -ldramsim -Wl,-rpath=$(DRAMSIM2_PATH)
DRAMSIM2_LIB := libdramsim.so DRAMSIM2_LIB := libdramsim.so
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala