riscv/rocket-chip
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test_mode_reset: use a cleaner interface with bundles and options instead of individual signals

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This commit is contained in:
Megan Wachs 2017-09-15 12:30:39 -07:00
parent ffc514d1bc
commit 6cda4504ac
4 changed files with 18 additions and 21 deletions
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6
src/main/scala/devices/debug/Debug.scala
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@ -1029,11 +1029,11 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip
// This comes from tlClk domain. // This comes from tlClk domain.
val debugUnavail = Vec(getNComponents(), Bool()).asInput val debugUnavail = Vec(getNComponents(), Bool()).asInput
val psd = new PSDTestModeIO() val psd = new PSDTestMode().asInput
} }
dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl) dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl)
dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd.test_mode, io.psd.test_mode_reset) dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd)
dmInner.module.io.debugUnavail := io.debugUnavail dmInner.module.io.debugUnavail := io.debugUnavail
} }
} }
@ -1067,7 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule {
val dmi = new ClockedDMIIO().flip val dmi = new ClockedDMIIO().flip
val in = node.bundleIn val in = node.bundleIn
val debugInterrupts = intnode.bundleOut val debugInterrupts = intnode.bundleOut
val psd = new PSDTestModeIO() val psd = new PSDTestMode()
} }
dmOuter.module.io.dmi <> io.dmi.dmi dmOuter.module.io.dmi <> io.dmi.dmi

4
src/main/scala/devices/debug/Periphery.scala
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@ -57,7 +57,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
val dtm = debug.systemjtag.map { sj => val dtm = debug.systemjtag.map { sj =>
val psd = debug.psd.getOrElse(Wire(init = new PSDTestModeIO().fromBits(0.U))) val psd = debug.psd.getOrElse(Wire(init = new PSDTestMode().fromBits(0.U)))
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey))) val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag dtm.io.jtag <> sj.jtag
@ -71,7 +71,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD
outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK
psd <> outer.debug.module.io.psd psd <> outer.debug.module.io.psd
outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd.test_mode, psd.test_mode_reset) outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd)
dtm dtm
} }

8
src/main/scala/util/PSDTestMode.scala
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@ -7,13 +7,13 @@ import freechips.rocketchip.config._
case object IncludePSDTest extends Field[Boolean](false) case object IncludePSDTest extends Field[Boolean](false)
class PSDTestModeIO extends Bundle { class PSDTestMode extends Bundle {
val test_mode = Bool(INPUT) val test_mode = Bool()
val test_mode_reset = Bool(INPUT) val test_mode_reset = Bool()
// TODO: Clocks? // TODO: Clocks?
} }
trait CanHavePSDTestModeIO { trait CanHavePSDTestModeIO {
implicit val p: Parameters implicit val p: Parameters
val psd = p(IncludePSDTest).option(new PSDTestModeIO()) val psd = p(IncludePSDTest).option(new PSDTestMode().asInput)
} }

21
src/main/scala/util/ResetCatchAndSync.scala
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@ -15,11 +15,10 @@ class ResetCatchAndSync (sync: Int = 3) extends Module {
val io = new Bundle { val io = new Bundle {
val sync_reset = Bool(OUTPUT) val sync_reset = Bool(OUTPUT)
val psd_test_reset = Bool(INPUT) val psd = new PSDTestMode().asInput
val psd_test_mode = Bool(INPUT)
} }
io.sync_reset := Mux(io.psd_test_mode, io.psd_test_reset, io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(Bool(true), sync)) ~AsyncResetSynchronizerShiftReg(Bool(true), sync))
} }
@ -27,24 +26,22 @@ class ResetCatchAndSync (sync: Int = 3) extends Module {
object ResetCatchAndSync { object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd_test_mode: Bool = Bool(false), psd_test_reset: Bool = Bool(false)): Bool = { psd: Option[PSDTestMode] =None): Bool = {
val catcher = Module (new ResetCatchAndSync(sync)) val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)} if (name.isDefined) {catcher.suggestName(name.get)}
catcher.clock := clk catcher.clock := clk
catcher.reset := rst catcher.reset := rst
catcher.io.psd_test_mode := psd_test_mode catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
catcher.io.psd_test_reset:= psd_test_reset
catcher.io.sync_reset catcher.io.sync_reset
} }
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name)) def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name)) def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, sync, Some(name), def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
psd_test_mode, psd_test_reset) apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, name = Some(name), def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
psd_test_mode = psd_test_mode, psd_test_reset = psd_test_reset) apply(clk, rst, name = Some(name), psd = Some(psd))
} }