From 6cda4504acd023ab77d8b88f1b03e8a6e0ec0876 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 15 Sep 2017 12:30:39 -0700 Subject: [PATCH] test_mode_reset: use a cleaner interface with bundles and options instead of individual signals --- src/main/scala/devices/debug/Debug.scala | 6 +++--- src/main/scala/devices/debug/Periphery.scala | 4 ++-- src/main/scala/util/PSDTestMode.scala | 8 ++++---- src/main/scala/util/ResetCatchAndSync.scala | 21 +++++++++----------- 4 files changed, 18 insertions(+), 21 deletions(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 8b0b9c70..fee423e7 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1029,11 +1029,11 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip // This comes from tlClk domain. val debugUnavail = Vec(getNComponents(), Bool()).asInput - val psd = new PSDTestModeIO() + val psd = new PSDTestMode().asInput } dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl) - dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd.test_mode, io.psd.test_mode_reset) + dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd) dmInner.module.io.debugUnavail := io.debugUnavail } } @@ -1067,7 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { val dmi = new ClockedDMIIO().flip val in = node.bundleIn val debugInterrupts = intnode.bundleOut - val psd = new PSDTestModeIO() + val psd = new PSDTestMode() } dmOuter.module.io.dmi <> io.dmi.dmi diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 3fd4ecf9..9a096c8f 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -57,7 +57,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD val dtm = debug.systemjtag.map { sj => - val psd = debug.psd.getOrElse(Wire(init = new PSDTestModeIO().fromBits(0.U))) + val psd = debug.psd.getOrElse(Wire(init = new PSDTestMode().fromBits(0.U))) val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag @@ -71,7 +71,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK psd <> outer.debug.module.io.psd - outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd.test_mode, psd.test_mode_reset) + outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd) dtm } diff --git a/src/main/scala/util/PSDTestMode.scala b/src/main/scala/util/PSDTestMode.scala index ae4a3942..c4898bf4 100644 --- a/src/main/scala/util/PSDTestMode.scala +++ b/src/main/scala/util/PSDTestMode.scala @@ -7,13 +7,13 @@ import freechips.rocketchip.config._ case object IncludePSDTest extends Field[Boolean](false) -class PSDTestModeIO extends Bundle { - val test_mode = Bool(INPUT) - val test_mode_reset = Bool(INPUT) +class PSDTestMode extends Bundle { + val test_mode = Bool() + val test_mode_reset = Bool() // TODO: Clocks? } trait CanHavePSDTestModeIO { implicit val p: Parameters - val psd = p(IncludePSDTest).option(new PSDTestModeIO()) + val psd = p(IncludePSDTest).option(new PSDTestMode().asInput) } diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index ab2f52f9..dc050a6b 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -15,11 +15,10 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { val io = new Bundle { val sync_reset = Bool(OUTPUT) - val psd_test_reset = Bool(INPUT) - val psd_test_mode = Bool(INPUT) + val psd = new PSDTestMode().asInput } - io.sync_reset := Mux(io.psd_test_mode, io.psd_test_reset, + io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset, ~AsyncResetSynchronizerShiftReg(Bool(true), sync)) } @@ -27,24 +26,22 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { object ResetCatchAndSync { def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, - psd_test_mode: Bool = Bool(false), psd_test_reset: Bool = Bool(false)): Bool = { + psd: Option[PSDTestMode] =None): Bool = { val catcher = Module (new ResetCatchAndSync(sync)) if (name.isDefined) {catcher.suggestName(name.get)} catcher.clock := clk catcher.reset := rst - catcher.io.psd_test_mode := psd_test_mode - catcher.io.psd_test_reset:= psd_test_reset - + catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0))) catcher.io.sync_reset } def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name)) def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name)) - def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, sync, Some(name), - psd_test_mode, psd_test_reset) - def apply(clk: Clock, rst: Bool, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, name = Some(name), - psd_test_mode = psd_test_mode, psd_test_reset = psd_test_reset) - + def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool = + apply(clk, rst, sync, Some(name), Some(psd)) + def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool = + apply(clk, rst, name = Some(name), psd = Some(psd)) + }