riscv/rocket-chip
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periphery: make external interrupts a UInt rather than a Vec[Bool]

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This commit is contained in:
Henry Cook
2017-02-23 11:48:49 -08:00
parent c01aec9259
commit 6c3011d513
2 changed files with 5 additions and 4 deletions
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3
src/main/scala/rocketchip/TestHarness.scala
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@ -15,8 +15,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
}
val dut = Module(LazyModule(new ExampleRocketTop).module)
for (int <- dut.io.interrupts(0))
int := Bool(false)
dut.io.interrupts := UInt(0)
val channels = p(coreplex.BankedL2Config).nMemoryChannels
if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4