riscv/rocket-chip
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periphery: make external interrupts a UInt rather than a Vec[Bool]

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This commit is contained in:
Henry Cook
2017-02-23 11:48:49 -08:00
parent c01aec9259
commit 6c3011d513
2 changed files with 5 additions and 4 deletions
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6
src/main/scala/rocketchip/Periphery.scala
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@ -48,7 +48,8 @@ trait HasPeripheryParameters {
trait PeripheryExtInterrupts {
this: TopNetwork =>
val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts))
val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts)
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode
@ -59,7 +60,7 @@ trait PeripheryExtInterruptsBundle {
this: TopNetworkBundle {
val outer: PeripheryExtInterrupts
} =>
val interrupts = outer.extInterrupts.bundleIn
val interrupts = UInt(INPUT, width = outer.nExtInterrupts)
}
trait PeripheryExtInterruptsModule {
@ -67,6 +68,7 @@ trait PeripheryExtInterruptsModule {
val outer: PeripheryExtInterrupts
val io: PeripheryExtInterruptsBundle
} =>
outer.extInterrupts.bundleIn(0).zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
}
/////