riscv/rocket-chip
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plic: do not output #address-cells

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This is only needed for an interrupt-map, not an interrupt-controller.
This commit is contained in:
Wesley W. Terpstra 2017-06-07 13:49:51 -07:00
parent 936096dd42
commit 6c2b770605
1 changed files with 1 additions and 2 deletions
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3
src/main/scala/uncore/devices/Plic.scala
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@ -70,8 +70,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
val extra = Map( val extra = Map(
"interrupt-controller" -> Nil, "interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,ndev" -> Seq(ResourceInt(nDevices)),
"#interrupt-cells" -> Seq(ResourceInt(1)), "#interrupt-cells" -> Seq(ResourceInt(1)))
"#address-cells" -> Seq(ResourceInt(0)))
Description(name, mapping ++ extra) Description(name, mapping ++ extra)
} }
} }