riscv/rocket-chip
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reduce D$ critical path through page table walker

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costs an extra cycle per page table level to resolve a TLB miss. too bad.
This commit is contained in:
Andrew Waterman 2012-03-16 17:14:43 -07:00
parent d38603a4ee
commit 6c26921766
1 changed files with 11 additions and 10 deletions
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19
rocket/src/main/scala/ptw.scala
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@ -109,10 +109,11 @@ class rocketPTW extends Component
req_addr := Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.itlb.req_vpn(VPN_BITS-1,VPN_BITS-10), Bits(0,3)).toUFix;
}
when (io.dmem.resp_val) {
req_addr := Cat(io.dmem.resp_data(PADDR_BITS-1, PGIDX_BITS), vpn_idx, Bits(0,3)).toUFix;
r_resp_perm := io.dmem.resp_data(9,4);
r_resp_ppn := io.dmem.resp_data(PADDR_BITS-1, PGIDX_BITS);
val dmem_resp_val = Reg(io.dmem.resp_val, resetVal = Bool(false))
when (dmem_resp_val) {
req_addr := Cat(io.dmem.resp_data_subword(PADDR_BITS-1, PGIDX_BITS), vpn_idx, Bits(0,3)).toUFix;
r_resp_perm := io.dmem.resp_data_subword(9,4);
r_resp_ppn := io.dmem.resp_data_subword(PADDR_BITS-1, PGIDX_BITS);
}
io.dmem.req_val :=
@ -129,8 +130,8 @@ class rocketPTW extends Component
val resp_val = (state === s_done) || (state === s_l1_fake) || (state === s_l2_fake);
val resp_err = (state === s_error);
val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2));
val resp_pte = (io.dmem.resp_data(1,0) === Bits(2,2));
val resp_ptd = (io.dmem.resp_data_subword(1,0) === Bits(1,2));
val resp_pte = (io.dmem.resp_data_subword(1,0) === Bits(2,2));
io.dtlb.req_rdy := (state === s_ready) && !io.itlb.req_val;
io.itlb.req_rdy := (state === s_ready);
@ -166,7 +167,7 @@ class rocketPTW extends Component
when (io.dmem.resp_nack) {
state := s_l1_req
}
when (io.dmem.resp_val) {
when (dmem_resp_val) {
when (resp_ptd) { // page table descriptor
state := s_l2_req;
}
@ -191,7 +192,7 @@ class rocketPTW extends Component
when (io.dmem.resp_nack) {
state := s_l2_req
}
when (io.dmem.resp_val) {
when (dmem_resp_val) {
when (resp_ptd) { // page table descriptor
state := s_l3_req;
}
@ -216,7 +217,7 @@ class rocketPTW extends Component
when (io.dmem.resp_nack) {
state := s_l3_req
}
when (io.dmem.resp_val) {
when (dmem_resp_val) {
when (resp_pte) { // page table entry
state := s_done;
}