hwacha integration: now it compiles correctly!
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@ -23,6 +23,7 @@ class ioMemArbiter extends Bundle() {
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val dcache = new ioDCache();
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// val icache = new ioICache();
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val icache = new ioIPrefetcherMem().flip();
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val vicache = new ioICache();
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}
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class rocketMemArbiter extends Component {
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@ -33,16 +34,23 @@ class rocketMemArbiter extends Component {
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// *****************************
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// Memory request is valid if either icache or dcache have a valid request
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io.mem.req_val := (io.icache.req_val || io.dcache.req_val);
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io.mem.req_val := (io.icache.req_val || io.vicache.req_val || io.dcache.req_val);
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// Set read/write bit. ICache always reads
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io.mem.req_rw := Mux(io.dcache.req_val, io.dcache.req_rw, Bool(false));
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// Give priority to ICache
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io.mem.req_addr := Mux(io.dcache.req_val, io.dcache.req_addr, io.icache.req_addr);
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io.mem.req_addr :=
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Mux(io.dcache.req_val, io.dcache.req_addr,
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Mux(io.icache.req_val, io.icache.req_addr,
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io.vicache.req_addr))
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// low bit of tag=0 for I$, 1 for D$
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io.mem.req_tag := Cat(Mux(io.dcache.req_val, io.dcache.req_tag, io.icache.req_tag), io.dcache.req_val)
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// low bit of tag to indicate D$, I$, and VI$
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val t_dcache :: t_icache :: t_vicache :: Nil = Enum(3){ UFix() }
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io.mem.req_tag :=
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Mux(io.dcache.req_val, Cat(io.dcache.req_tag, t_dcache),
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Mux(io.icache.req_val, Cat(io.icache.req_tag, t_icache),
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Cat(Bits(0, MEM_TAG_BITS-2), t_vicache)))
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// Just pass through write data (only D$ will write)
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io.mem.req_wdata := io.dcache.req_wdata;
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@ -55,18 +63,20 @@ class rocketMemArbiter extends Component {
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// This way, writebacks will never be interrupted by I$ refills.
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io.dcache.req_rdy := io.mem.req_rdy;
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io.icache.req_rdy := io.mem.req_rdy && !io.dcache.req_val;
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io.vicache.req_rdy := io.mem.req_rdy && !io.dcache.req_val && !io.icache.req_val
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// Response will only be valid for D$ or I$ not both because of tag bits
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io.icache.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
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io.dcache.resp_val := io.mem.resp_val && io.mem.resp_tag(0).toBool;
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io.dcache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_dcache)
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io.icache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_icache)
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io.vicache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_vicache)
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// Feed through data to both
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io.icache.resp_data := io.mem.resp_data;
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io.dcache.resp_data := io.mem.resp_data;
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io.icache.resp_data := io.mem.resp_data;
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io.vicache.resp_data := io.mem.resp_data
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io.icache.resp_tag := io.mem.resp_tag >> UFix(1)
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io.dcache.resp_tag := io.mem.resp_tag >> UFix(1)
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io.dcache.resp_tag := io.mem.resp_tag >> UFix(2)
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io.icache.resp_tag := io.mem.resp_tag >> UFix(2)
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}
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}
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@ -177,7 +177,7 @@ object Constants
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// external memory interface
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val IMEM_TAG_BITS = 1;
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val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;
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val MEM_TAG_BITS = 1 + max(IMEM_TAG_BITS, DMEM_TAG_BITS);
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val MEM_TAG_BITS = 2 + max(IMEM_TAG_BITS, DMEM_TAG_BITS);
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val MEM_DATA_BITS = 128;
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS;
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@ -30,6 +30,7 @@ class ioRocket extends Bundle()
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val console = new ioConsole();
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val host = new ioHost();
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val imem = new ioImem().flip();
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val vimem = new ioImem().flip();
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val dmem = new ioDmem().flip();
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}
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@ -42,6 +43,7 @@ class rocketProc extends Component
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val dtlb = new rocketDTLB(DTLB_ENTRIES);
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val itlb = new rocketITLB(ITLB_ENTRIES);
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val vitlb = new rocketITLB(ITLB_ENTRIES);
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val ptw = new rocketPTW();
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val arb = new rocketDmemArbiter();
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@ -130,8 +132,36 @@ class rocketProc extends Component
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{
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val vu = new vu()
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vitlb.io.cpu.invalidate := dpath.io.ptbr_wen
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vitlb.io.cpu.status := dpath.io.ctrl.status
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vitlb.io.cpu.req_val := vu.io.imem_req.valid
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vitlb.io.cpu.req_asid := Bits(0,ASID_BITS) // FIXME: connect to PCR
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vitlb.io.cpu.req_vpn := vu.io.imem_req.bits(VADDR_BITS,PGIDX_BITS).toUFix
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io.vimem.req_idx := vu.io.imem_req.bits(PGIDX_BITS-1,0)
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io.vimem.req_ppn := vitlb.io.cpu.resp_ppn
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io.vimem.req_val := vu.io.imem_req.valid
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io.vimem.invalidate := ctrl.io.dpath.flush_inst
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vu.io.imem_resp.valid := io.vimem.resp_val
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vu.io.imem_resp.bits := io.vimem.resp_data
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// handle vitlb.io.cpu.exception
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io.vimem.itlb_miss := vitlb.io.cpu.resp_miss
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vu.io.vec_cmdq <> dpath.io.vcmdq
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vu.io.vec_ximm1q <> dpath.io.vximm1q
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vu.io.vec_ximm2q <> dpath.io.vximm2q
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ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
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ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd
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ctrl.io.ext_mem.req_type := vu.io.dmem_req.bits.typ
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dpath.io.ext_mem.req_val := vu.io.dmem_req.valid
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dpath.io.ext_mem.req_idx := vu.io.dmem_req.bits.idx
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dpath.io.ext_mem.req_ppn := vu.io.dmem_req.bits.ppn
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dpath.io.ext_mem.req_data := vu.io.dmem_req.bits.data
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vu.io.dmem_resp.valid := dpath.io.ext_mem.resp_val
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vu.io.dmem_resp.bits.nack := ctrl.io.ext_mem.resp_nack
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vu.io.dmem_resp.bits.data := dpath.io.ext_mem.resp_data
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vu.io.dmem_resp.bits.tag := dpath.io.ext_mem.resp_tag
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}
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}
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@ -34,7 +34,7 @@ class ioDpathAll extends Bundle()
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val console = new ioConsole(List("valid","bits"));
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val debug = new ioDebug();
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val dmem = new ioDpathDmem();
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val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "resp_val", "resp_data", "resp_tag"))
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val ext_mem = new ioDmem(List("req_val", "req_idx", "req_ppn", "req_data", "req_tag", "resp_val", "resp_data", "resp_tag"))
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val imem = new ioDpathImem();
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val vcmdq = new io_vec_cmdq()
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val vximm1q = new io_vec_ximm1q()
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@ -101,6 +101,7 @@ class rocketDpath extends Component
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val ex_reg_ctrl_sel_wb = Reg() { UFix() };
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val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
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val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
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val ex_reg_ext_mem_tag = Reg() { Bits() };
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val ex_wdata = Wire() { Bits() };
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// memory definitions
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@ -251,6 +252,7 @@ class rocketDpath extends Component
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ex_reg_ctrl_div_fn := io.ctrl.div_fn;
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ex_reg_ctrl_sel_wb := io.ctrl.sel_wb;
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ex_reg_ctrl_ren_pcr := io.ctrl.ren_pcr;
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ex_reg_ext_mem_tag := io.ext_mem.req_tag
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when(io.ctrl.killd) {
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ex_reg_valid := Bool(false);
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@ -306,7 +308,7 @@ class rocketDpath extends Component
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req_addr := ex_effective_address.toUFix;
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io.dmem.req_data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
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io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val, io.ctrl.ex_ext_mem_val).toUFix
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io.dmem.req_tag := Cat(Mux(io.ctrl.ex_ext_mem_val, ex_reg_ext_mem_tag(CPU_TAG_BITS-2, 0), Cat(ex_reg_waddr, io.ctrl.ex_fp_val)), io.ctrl.ex_ext_mem_val).toUFix
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// processor control regfile read
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pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;
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@ -17,12 +17,14 @@ class Top() extends Component {
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val cpu = new rocketProc();
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val icache = new rocketICache(128, 2); // 128 sets x 2 ways
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val icache_pf = new rocketIPrefetcher();
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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val dcache = new HellaCache();
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val arbiter = new rocketMemArbiter();
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arbiter.io.mem <> io.mem;
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arbiter.io.dcache <> dcache.io.mem;
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arbiter.io.icache <> icache_pf.io.mem;
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arbiter.io.vicache <> vicache.io.mem
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cpu.io.host <> io.host;
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cpu.io.debug <> io.debug;
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@ -30,6 +32,7 @@ class Top() extends Component {
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icache.io.mem <> icache_pf.io.icache;
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cpu.io.imem <> icache.io.cpu;
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cpu.io.vimem <> vicache.io.cpu;
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cpu.io.dmem <> dcache.io.cpu;
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}
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