pull out prefetch commands from isRead
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@ -63,7 +63,8 @@ trait MemoryOpConstants {
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val M_XA_MAXU = Bits("b1111", 4);
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val M_XA_MAXU = Bits("b1111", 4);
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def isAMO(cmd: Bits) = cmd(3)
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def isAMO(cmd: Bits) = cmd(3)
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def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_PFR || cmd === M_PFW || isAMO(cmd)
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def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
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def isRead(cmd: Bits) = cmd === M_XRD || isAMO(cmd)
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def isWrite(cmd: Bits) = cmd === M_XWR || isAMO(cmd)
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def isWrite(cmd: Bits) = cmd === M_XWR || isAMO(cmd)
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}
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}
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