riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

pull out prefetch commands from isRead

Browse Source
This commit is contained in:
Yunsup Lee committed 2012-11-18 03:13:17 -08:00
1 parent 3e6dc35809
commit 6bd4f93f8c
1 file changed
+2 -1
Download Patch File Download Diff File Expand all files Collapse all files
uncore/src/consts.scala
+2 -1
View File
@@ -63,7 +63,8 @@ trait MemoryOpConstants {
val M_XA_MAXU = Bits("b1111", 4);
def isAMO(cmd: Bits) = cmd(3)
def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_PFR || cmd === M_PFW || isAMO(cmd)
def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: Bits) = cmd === M_XRD || isAMO(cmd)
def isWrite(cmd: Bits) = cmd === M_XWR || isAMO(cmd)
}