changed coherence message type names
This commit is contained in:
parent
27e3346c14
commit
6bc47a55b4
@ -4,7 +4,7 @@ import Chisel._
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import Constants._
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class TransactionInit extends Bundle {
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val t_type = Bits(width = X_INIT_TYPE_BITS)
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val x_type = Bits(width = X_INIT_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = UFix(width = PADDR_BITS - OFFSET_BITS)
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}
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@ -29,7 +29,7 @@ class ProbeReply extends Bundle {
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class ProbeReplyData extends MemData
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class TransactionReply extends MemData {
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val t_type = Bits(width = X_REP_TYPE_BITS)
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val x_type = Bits(width = X_REP_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val require_ack = Bool()
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@ -54,13 +54,13 @@ trait CoherencePolicy { }
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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val X_INIT_READ_SHARED = UFix(0, 2)
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val X_INIT_READ_EXCLUSIVE = UFix(1, 2)
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val X_INIT_WRITE_UNCACHED = UFix(3, 2)
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val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
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val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
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val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
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val xactInitReadShared = UFix(0, 2)
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val xactInitReadExclusive = UFix(1, 2)
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val xactInitWriteUncached = UFix(3, 2)
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val xactReplyReadShared = UFix(0, X_REP_TYPE_BITS)
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val xactReplyReadExclusive = UFix(1, X_REP_TYPE_BITS)
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val xactReplyWriteUncached = UFix(3, X_REP_TYPE_BITS)
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val probeRepInvalidateAck = UFix(3, P_REP_TYPE_BITS)
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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@ -84,55 +84,36 @@ trait ThreeStateIncoherence extends CoherencePolicy {
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
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Mux(write, xactInitReadExclusive, outstanding.x_type)
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileDirty, tileClean)
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Mux(outstanding.x_type === xactInitReadExclusive, tileDirty, tileClean)
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, has_data: Bool): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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reply.p_type := P_REP_INVALIDATE_ACK
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reply.p_type := probeRepInvalidateAck
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reply.global_xact_id := UFix(0)
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reply
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}
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.t_type === X_INIT_WRITE_UNCACHED)
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def transactionInitHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteUncached)
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}
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trait FourStateCoherence extends CoherencePolicy {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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val X_INIT_READ_SHARED = UFix(0, X_INIT_TYPE_BITS)
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val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS)
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val X_INIT_READ_UNCACHED = UFix(2, X_INIT_TYPE_BITS)
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val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS)
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val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
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val X_REP_READ_UNCACHED = UFix(2, X_REP_TYPE_BITS)
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val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS)
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val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS)
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val P_REQ_DOWNGRADE = UFix(1, P_REQ_TYPE_BITS)
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val P_REQ_COPY = UFix(2, P_REQ_TYPE_BITS)
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val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS)
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val P_REP_DOWNGRADE_DATA = UFix(1, P_REP_TYPE_BITS)
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val P_REP_COPY_DATA = UFix(2, P_REP_TYPE_BITS)
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val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
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val P_REP_DOWNGRADE_ACK = UFix(4, P_REP_TYPE_BITS)
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val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
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val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
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val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(5){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
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def isHit (cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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@ -145,8 +126,8 @@ trait FourStateCoherence extends CoherencePolicy {
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) ||
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(write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE))
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(read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
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(write && (outstanding.x_type != xactInitReadExclusive))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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MuxLookup(cmd, (state === tileExclusiveDirty), Array(
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@ -171,44 +152,44 @@ trait FourStateCoherence extends CoherencePolicy {
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def newStateOnWriteback() = newStateOnCacheControl(M_INV)
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def newStateOnFlush() = newStateOnCacheControl(M_INV)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.t_type, tileInvalid, Array(
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X_REP_READ_SHARED -> tileShared,
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X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
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X_REP_READ_EXCLUSIVE_ACK -> tileExclusiveDirty,
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X_REP_READ_UNCACHED -> tileInvalid,
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X_REP_WRITE_UNCACHED -> tileInvalid
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyReadShared -> tileShared,
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xactReplyReadExclusive -> Mux(outstanding.x_type === xactInitReadExclusive, tileExclusiveDirty, tileExclusiveClean),
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xactReplyReadExclusiveAck -> tileExclusiveDirty,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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probeInvalidate -> tileInvalid,
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probeDowngrade -> tileShared,
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probeCopy -> state
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probeReqInvalidate -> tileInvalid,
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probeReqDowngrade -> tileShared,
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probeReqCopy -> state
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))
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}
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
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Mux(write, xactInitReadExclusive, outstanding.x_type)
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}
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = X_INIT_WRITE_UNCACHED
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val with_data = MuxLookup(incoming.p_type, P_REP_INVALIDATE_DATA, Array(
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probeInvalidate -> P_REP_INVALIDATE_DATA,
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probeDowngrade -> P_REP_DOWNGRADE_DATA,
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probeCopy -> P_REP_COPY_DATA
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqDowngrade -> probeRepDowngradeData,
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probeReqCopy -> probeRepCopyData
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))
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val without_data = MuxLookup(incoming.p_type, P_REP_INVALIDATE_ACK, Array(
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probeInvalidate -> P_REP_INVALIDATE_ACK,
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probeDowngrade -> P_REP_DOWNGRADE_ACK,
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probeCopy -> P_REP_COPY_ACK
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val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
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probeReqInvalidate -> probeRepInvalidateAck,
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probeReqDowngrade -> probeRepDowngradeAck,
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probeReqCopy -> probeRepCopyAck
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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@ -216,44 +197,44 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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def hasData (reply: ProbeReply): Bool = {
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(reply.p_type === P_REP_INVALIDATE_DATA ||
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reply.p_type === P_REP_DOWNGRADE_DATA ||
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reply.p_type === P_REP_COPY_DATA)
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(reply.p_type === probeRepInvalidateData ||
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reply.p_type === probeRepDowngradeData ||
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reply.p_type === probeRepCopyData)
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}
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def hasData (init: TransactionInit): Bool = {
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(init.t_type === X_INIT_WRITE_UNCACHED)
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(init.x_type === xactInitWriteUncached)
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}
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def hasData (reply: TransactionReply): Bool = {
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(reply.t_type != X_REP_WRITE_UNCACHED && reply.t_type != X_REP_READ_EXCLUSIVE_ACK)
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
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}
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
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MuxLookup(t_type, X_REP_READ_UNCACHED, Array(
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X_INIT_READ_SHARED -> Mux(count > UFix(0), X_REP_READ_SHARED, X_REP_READ_EXCLUSIVE),
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X_INIT_READ_EXCLUSIVE -> X_REP_READ_EXCLUSIVE,
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X_INIT_READ_UNCACHED -> X_REP_READ_UNCACHED,
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X_INIT_WRITE_UNCACHED -> X_REP_WRITE_UNCACHED
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
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MuxLookup(x_type, xactReplyReadUncached, Array(
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xactInitReadShared -> Mux(count > UFix(0), xactReplyReadShared, xactReplyReadExclusive),
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xactInitReadExclusive -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached
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))
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}
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def getProbeRequestType(t_type: UFix, global_state: UFix): UFix = {
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MuxLookup(t_type, P_REQ_COPY, Array(
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X_INIT_READ_SHARED -> P_REQ_DOWNGRADE,
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X_INIT_READ_EXCLUSIVE -> P_REQ_INVALIDATE,
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X_INIT_READ_UNCACHED -> P_REQ_COPY,
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X_INIT_WRITE_UNCACHED -> P_REQ_INVALIDATE
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
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MuxLookup(x_type, probeReqCopy, Array(
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xactInitReadShared -> probeReqDowngrade,
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xactInitReadExclusive -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate
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))
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}
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def needsMemRead(t_type: UFix, global_state: UFix): Bool = {
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(t_type != X_INIT_WRITE_UNCACHED)
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def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
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(x_type != xactInitWriteUncached)
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}
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def needsMemWrite(t_type: UFix, global_state: UFix): Bool = {
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(t_type === X_INIT_WRITE_UNCACHED)
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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def needsAckReply(t_type: UFix, global_state: UFix): Bool = {
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(t_type === X_INIT_WRITE_UNCACHED)
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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}
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@ -74,7 +74,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT)
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val t_type = Bits(X_INIT_TYPE_BITS, OUTPUT)
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val x_type = Bits(X_INIT_TYPE_BITS, OUTPUT)
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val push_p_req = Bits(ntiles, OUTPUT)
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val pop_p_rep = Bits(ntiles, OUTPUT)
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val pop_p_rep_data = Bits(ntiles, OUTPUT)
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@ -117,7 +117,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val addr_ = Reg{ UFix() }
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val t_type_ = Reg{ Bits() }
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val x_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val p_rep_count = if (ntiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(ntiles)))
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@ -138,7 +138,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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io.p_rep_tile_id := p_rep_tile_id_
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io.tile_xact_id := tile_xact_id_
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io.sharer_count := UFix(ntiles) // TODO: Broadcast only
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io.t_type := t_type_
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io.x_type := x_type_
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io.mem_req_cmd.valid := Bool(false)
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io.mem_req_cmd.bits.rw := Bool(false)
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@ -148,7 +148,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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io.mem_req_data.bits.data := UFix(0)
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io.mem_req_lock := Bool(false)
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io.probe_req.valid := Bool(false)
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io.probe_req.bits.p_type := getProbeRequestType(t_type_, UFix(0))
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io.probe_req.bits.p_type := getProbeRequestType(x_type_, UFix(0))
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io.probe_req.bits.global_xact_id := UFix(id)
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io.probe_req.bits.address := addr_
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io.push_p_req := Bits(0, width = ntiles)
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@ -164,11 +164,11 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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is(s_idle) {
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when( io.alloc_req.valid && io.can_alloc ) {
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addr_ := io.alloc_req.bits.xact_init.address
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t_type_ := io.alloc_req.bits.xact_init.t_type
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x_type_ := io.alloc_req.bits.xact_init.x_type
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init_tile_id_ := io.alloc_req.bits.tile_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := hasData(io.alloc_req.bits.xact_init)
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.x_type, UFix(0))
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if(ntiles > 1) p_rep_count := UFix(ntiles-1)
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val p_req_initial_flags = ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
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p_req_flags := p_req_initial_flags
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@ -226,7 +226,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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state := Mux(needsAckReply(t_type_, UFix(0)), s_ack, s_busy)
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state := Mux(needsAckReply(x_type_, UFix(0)), s_ack, s_busy)
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}
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}
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is(s_ack) {
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@ -251,7 +251,7 @@ abstract class CoherenceHub(ntiles: Int) extends Component with CoherencePolicy
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class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
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{
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val x_init = io.tiles(0).xact_init
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val is_write = x_init.bits.t_type === X_INIT_WRITE_UNCACHED
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val is_write = x_init.bits.x_type === xactInitWriteUncached
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x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
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io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
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io.mem.req_cmd.bits.rw := is_write
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@ -260,7 +260,7 @@ class CoherenceHubNull extends CoherenceHub(1) with ThreeStateIncoherence
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io.mem.req_data <> io.tiles(0).xact_init_data
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val x_rep = io.tiles(0).xact_rep
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x_rep.bits.t_type := Mux(io.mem.resp.valid, X_REP_READ_EXCLUSIVE, X_REP_WRITE_UNCACHED)
|
||||
x_rep.bits.x_type := Mux(io.mem.resp.valid, xactReplyReadExclusive, xactReplyWriteUncached)
|
||||
x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
|
||||
x_rep.bits.global_xact_id := UFix(0) // don't care
|
||||
x_rep.bits.data := io.mem.resp.bits.data
|
||||
@ -283,7 +283,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
|
||||
val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
|
||||
val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
|
||||
val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
|
||||
val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} }
|
||||
val x_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} }
|
||||
val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
|
||||
val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
|
||||
|
||||
@ -300,7 +300,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
|
||||
addr_arr(i) := t.addr
|
||||
init_tile_id_arr(i) := t.init_tile_id
|
||||
tile_xact_id_arr(i) := t.tile_xact_id
|
||||
t_type_arr(i) := t.t_type
|
||||
x_type_arr(i) := t.x_type
|
||||
sh_count_arr(i) := t.sharer_count
|
||||
send_x_rep_ack_arr(i) := t.send_x_rep_ack
|
||||
t.xact_finish := do_free_arr(i)
|
||||
@ -337,19 +337,19 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
|
||||
val ack_idx = PriorityEncoder(send_x_rep_ack_arr.toBits)
|
||||
for( j <- 0 until ntiles ) {
|
||||
val rep = io.tiles(j).xact_rep
|
||||
rep.bits.t_type := UFix(0)
|
||||
rep.bits.x_type := UFix(0)
|
||||
rep.bits.tile_xact_id := UFix(0)
|
||||
rep.bits.global_xact_id := UFix(0)
|
||||
rep.bits.data := io.mem.resp.bits.data
|
||||
rep.bits.require_ack := Bool(true)
|
||||
rep.valid := Bool(false)
|
||||
when(io.mem.resp.valid && (UFix(j) === init_tile_id_arr(mem_idx))) {
|
||||
rep.bits.t_type := getTransactionReplyType(t_type_arr(mem_idx), sh_count_arr(mem_idx))
|
||||
rep.bits.x_type := getTransactionReplyType(x_type_arr(mem_idx), sh_count_arr(mem_idx))
|
||||
rep.bits.tile_xact_id := tile_xact_id_arr(mem_idx)
|
||||
rep.bits.global_xact_id := mem_idx
|
||||
rep.valid := Bool(true)
|
||||
} . otherwise {
|
||||
rep.bits.t_type := getTransactionReplyType(t_type_arr(ack_idx), sh_count_arr(ack_idx))
|
||||
rep.bits.x_type := getTransactionReplyType(x_type_arr(ack_idx), sh_count_arr(ack_idx))
|
||||
rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
|
||||
rep.bits.global_xact_id := ack_idx
|
||||
when (UFix(j) === init_tile_id_arr(ack_idx)) {
|
||||
|
Loading…
Reference in New Issue
Block a user