241 lines
9.2 KiB
Scala
241 lines
9.2 KiB
Scala
package rocket
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import Chisel._
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import Constants._
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class TransactionInit extends Bundle {
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val x_type = Bits(width = X_INIT_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = UFix(width = PADDR_BITS - OFFSET_BITS)
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}
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class TransactionInitData extends MemData
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class TransactionAbort extends Bundle {
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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}
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class ProbeRequest extends Bundle {
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val p_type = Bits(width = P_REQ_TYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS - OFFSET_BITS)
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}
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class ProbeReply extends Bundle {
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val p_type = Bits(width = P_REP_TYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends MemData
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class TransactionReply extends MemData {
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val x_type = Bits(width = X_REP_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val require_ack = Bool()
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}
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class TransactionFinish extends Bundle {
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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object cpuCmdToRW {
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def apply(cmd: Bits): (Bool, Bool) = {
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val store = (cmd === M_XWR)
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val load = (cmd === M_XRD)
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val amo = cmd(3).toBool
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val read = load || amo || (cmd === M_PFR) || (cmd === M_PFW)
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val write = store || amo
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(read, write)
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}
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}
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trait CoherencePolicy { }
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trait ThreeStateIncoherence extends CoherencePolicy {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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val xactInitReadShared = UFix(0, 2)
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val xactInitReadExclusive = UFix(1, 2)
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val xactInitWriteUncached = UFix(3, 2)
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val xactReplyReadShared = UFix(0, X_REP_TYPE_BITS)
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val xactReplyReadExclusive = UFix(1, X_REP_TYPE_BITS)
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val xactReplyWriteUncached = UFix(3, X_REP_TYPE_BITS)
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val probeRepInvalidateAck = UFix(3, P_REP_TYPE_BITS)
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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( state === tileClean || state === tileDirty)
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnCacheControl(cmd: Bits) = tileInvalid
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def newState(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, xactInitReadExclusive, outstanding.x_type)
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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Mux(outstanding.x_type === xactInitReadExclusive, tileDirty, tileClean)
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, has_data: Bool): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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reply.p_type := probeRepInvalidateAck
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reply.global_xact_id := UFix(0)
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reply
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}
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.x_type === xactInitWriteUncached)
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}
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trait FourStateCoherence extends CoherencePolicy {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val xactInitReadShared :: xactInitReadExclusive :: xactInitReadUncached :: xactInitWriteUncached :: Nil = Enum(4){ UFix() }
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val xactReplyReadShared :: xactReplyReadExclusive :: xactReplyReadUncached :: xactReplyWriteUncached :: xactReplyReadExclusiveAck :: Nil = Enum(5){ UFix() }
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val probeReqInvalidate :: probeReqDowngrade :: probeReqCopy :: Nil = Enum(3){ UFix() }
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val probeRepInvalidateData :: probeRepDowngradeData :: probeRepCopyData :: probeRepInvalidateAck :: probeRepDowngradeAck :: probeRepCopyAck :: Nil = Enum(6){ UFix() }
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def isHit (cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
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(state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsTransactionOnSecondaryMiss(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.x_type === xactInitReadUncached || outstanding.x_type === xactInitWriteUncached)) ||
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(write && (outstanding.x_type != xactInitReadExclusive))
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}
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def needsTransactionOnCacheControl(cmd: Bits, state: UFix): Bool = {
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MuxLookup(cmd, (state === tileExclusiveDirty), Array(
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M_INV -> (state === tileExclusiveDirty),
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M_CLN -> (state === tileExclusiveDirty)
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))
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}
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def needsWriteback (state: UFix): Bool = {
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needsTransactionOnCacheControl(M_INV, state)
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileExclusiveDirty, state)
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}
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def newStateOnCacheControl(cmd: Bits) = {
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MuxLookup(cmd, tileInvalid, Array(
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M_INV -> tileInvalid,
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M_CLN -> tileExclusiveClean
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))
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}
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def newStateOnWriteback() = newStateOnCacheControl(M_INV)
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def newStateOnFlush() = newStateOnCacheControl(M_INV)
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def newStateOnTransactionReply(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.x_type, tileInvalid, Array(
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xactReplyReadShared -> tileShared,
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xactReplyReadExclusive -> Mux(outstanding.x_type === xactInitReadExclusive, tileExclusiveDirty, tileExclusiveClean),
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xactReplyReadExclusiveAck -> tileExclusiveDirty,
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xactReplyReadUncached -> tileInvalid,
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xactReplyWriteUncached -> tileInvalid
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))
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}
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def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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probeReqInvalidate -> tileInvalid,
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probeReqDowngrade -> tileShared,
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probeReqCopy -> state
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))
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}
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def getTransactionInitTypeOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write || cmd === M_PFW, xactInitReadExclusive, xactInitReadShared)
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}
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def getTransactionInitTypeOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, xactInitReadExclusive, outstanding.x_type)
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}
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def getTransactionInitTypeOnCacheControl(cmd: Bits): Bits = xactInitWriteUncached
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def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
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probeReqInvalidate -> probeRepInvalidateData,
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probeReqDowngrade -> probeRepDowngradeData,
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probeReqCopy -> probeRepCopyData
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))
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val without_data = MuxLookup(incoming.p_type, probeRepInvalidateAck, Array(
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probeReqInvalidate -> probeRepInvalidateAck,
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probeReqDowngrade -> probeRepDowngradeAck,
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probeReqCopy -> probeRepCopyAck
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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reply
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}
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def hasData (reply: ProbeReply): Bool = {
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(reply.p_type === probeRepInvalidateData ||
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reply.p_type === probeRepDowngradeData ||
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reply.p_type === probeRepCopyData)
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}
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def hasData (init: TransactionInit): Bool = {
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(init.x_type === xactInitWriteUncached)
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}
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def hasData (reply: TransactionReply): Bool = {
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(reply.x_type != xactReplyWriteUncached && reply.x_type != xactReplyReadExclusiveAck)
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}
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def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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def getTransactionReplyType(x_type: UFix, count: UFix): Bits = {
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MuxLookup(x_type, xactReplyReadUncached, Array(
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xactInitReadShared -> Mux(count > UFix(0), xactReplyReadShared, xactReplyReadExclusive),
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xactInitReadExclusive -> xactReplyReadExclusive,
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xactInitReadUncached -> xactReplyReadUncached,
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xactInitWriteUncached -> xactReplyWriteUncached
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))
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}
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def getProbeRequestType(x_type: UFix, global_state: UFix): UFix = {
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MuxLookup(x_type, probeReqCopy, Array(
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xactInitReadShared -> probeReqDowngrade,
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xactInitReadExclusive -> probeReqInvalidate,
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xactInitReadUncached -> probeReqCopy,
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xactInitWriteUncached -> probeReqInvalidate
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))
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}
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def needsMemRead(x_type: UFix, global_state: UFix): Bool = {
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(x_type != xactInitWriteUncached)
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}
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def needsMemWrite(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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def needsAckReply(x_type: UFix, global_state: UFix): Bool = {
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(x_type === xactInitWriteUncached)
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}
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}
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