riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

flip direction of ioPipe to match ioDecoupled

Browse Source
This commit is contained in:
Andrew Waterman 2012-03-02 16:18:32 -08:00
parent 9ad4fd5814
commit 6ad7aa5cdc
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
uncore/coherence.scala
View File

@ -23,7 +23,7 @@ class ioMem() extends Bundle
{ {
val req_cmd = (new ioDecoupled) { new MemReqCmd() } val req_cmd = (new ioDecoupled) { new MemReqCmd() }
val req_data = (new ioDecoupled) { new MemData() } val req_data = (new ioDecoupled) { new MemData() }
val resp = (new ioPipe) { new MemResp() } val resp = (new ioPipe) { new MemResp() }.flip
} }
class HubMemReq extends Bundle { class HubMemReq extends Bundle {
@ -86,7 +86,7 @@ class ioTileLink extends Bundle {
val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
val probe_rep = (new ioDecoupled) { new ProbeReply() } val probe_rep = (new ioDecoupled) { new ProbeReply() }
val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() } val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }
val xact_rep = (new ioPipe) { new TransactionReply() } val xact_rep = (new ioPipe) { new TransactionReply() }.flip
val xact_finish = (new ioDecoupled) { new TransactionFinish() } val xact_finish = (new ioDecoupled) { new TransactionFinish() }
} }