riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

plusarg_reader: support verilator

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-05-18 22:54:40 -07:00
parent 9eae1fa377
commit 6a7e6ab325
1 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
vsrc/plusarg_reader.v
View File

@ -10,13 +10,11 @@ reg [31:0] myplus;
assign out = myplus; assign out = myplus;
initial begin initial begin
`ifdef SYNTHESIS
myplus = DEFAULT; myplus = DEFAULT;
`ifndef SYNTHESIS `else
`ifndef verilator
// Work-around for https://www.veripool.org/issues/1165
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT; if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
`endif `endif
`endif
end end
endmodule endmodule