riscv/rocket-chip
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fix assembly tests for configurations without VMU and/or user mode

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This commit is contained in:
Howard Mao 2016-07-22 11:36:45 -07:00
parent 75347eed56
commit 6a5b2d7f59
5 changed files with 15 additions and 9 deletions
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2
regression/Makefile
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@ -44,7 +44,7 @@ $(error Set SUITE to the regression suite you want to run)
endif endif
ifeq ($(SUITE),RocketSuite) ifeq ($(SUITE),RocketSuite)
CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig RoccExampleConfig CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig RoccExampleConfig
endif endif
ifeq ($(SUITE),GroundtestSuite) ifeq ($(SUITE),GroundtestSuite)

2
riscv-tools

@ -1 +1 @@
Subproject commit 6953e5c4a32afd0055200578a3e7eda064f58859 Subproject commit 7219be435a89277603e566e806ae8540c7f9a917

2
rocket

@ -1 +1 @@
Subproject commit 5c6f470ef4b5eba3a654b37a0b1767a25a5be437 Subproject commit 94e2174ab654e0458a2d7cdc02980a0991299c9f

10
src/main/scala/Configs.scala
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@ -169,11 +169,11 @@ class BaseConfig extends Config (
//Tile Constants //Tile Constants
case BuildTiles => { case BuildTiles => {
val (rvi, rvu) = val (rvi, rvu) =
if (site(XLen) == 64) (rv64i, rv64u) if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
else (rv32i, rv32u) else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p"))) TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env)))) TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks) TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
List.fill(site(NTiles)){ (r: Bool, p: Parameters) => List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({ Module(new RocketTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2" case TLId => "L1toL2"
@ -569,3 +569,7 @@ class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new De
class DualCoreConfig extends Config( class DualCoreConfig extends Config(
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig) new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
class TinyConfig extends Config(
new WithRV32 ++ new WithSmallCores ++
new WithStatelessBridge ++ new BaseConfig)

8
src/main/scala/Testing.scala
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@ -105,14 +105,15 @@ object DefaultTestSuites {
val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w") val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w")
val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_) val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_)
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi") val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi", "dirty")
val rv32si = new AssemblyTestSuite("rv32si", rv32siNames)(_) val rv32si = new AssemblyTestSuite("rv32si", rv32siNames)(_)
val rv32miNames = LinkedHashSet("breakpoint", "csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall") val rv32miNames = LinkedHashSet("csr", "mcsr", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32mi = new AssemblyTestSuite("rv32mi", rv32miNames)(_) val rv32mi = new AssemblyTestSuite("rv32mi", rv32miNames)(_)
val rv32u = List(rv32ui, rv32um) val rv32u = List(rv32ui, rv32um)
val rv32i = List(rv32ui, rv32si, rv32mi) val rv32i = List(rv32ui, rv32si, rv32mi)
val rv32pi = List(rv32ui, rv32mi)
val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw") val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw")
val rv64ui = new AssemblyTestSuite("rv64ui", rv32uiNames ++ rv64uiNames)(_) val rv64ui = new AssemblyTestSuite("rv64ui", rv32uiNames ++ rv64uiNames)(_)
@ -134,7 +135,7 @@ object DefaultTestSuites {
val rv64siNames = rv32siNames val rv64siNames = rv32siNames
val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_) val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
val rv64miNames = rv32miNames val rv64miNames = rv32miNames + "breakpoint"
val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_) val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_)
val groundtestNames = LinkedHashSet("simple") val groundtestNames = LinkedHashSet("simple")
@ -145,6 +146,7 @@ object DefaultTestSuites {
val rv64u = List(rv64ui, rv64um) val rv64u = List(rv64ui, rv64um)
val rv64i = List(rv64ui, rv64si, rv64mi) val rv64i = List(rv64ui, rv64si, rv64mi)
val rv64pi = List(rv64ui, rv64mi)
val benchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet( val benchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet(
"median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul")) "median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul"))