From 6a5b2d7f591514f24a8d799e20593b3bc5a3e8b9 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 22 Jul 2016 11:36:45 -0700 Subject: [PATCH] fix assembly tests for configurations without VMU and/or user mode --- regression/Makefile | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/Configs.scala | 10 +++++++--- src/main/scala/Testing.scala | 8 +++++--- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/regression/Makefile b/regression/Makefile index 3444730c..60d9bbba 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -44,7 +44,7 @@ $(error Set SUITE to the regression suite you want to run) endif ifeq ($(SUITE),RocketSuite) -CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig RoccExampleConfig +CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig TinyConfig RoccExampleConfig endif ifeq ($(SUITE),GroundtestSuite) diff --git a/riscv-tools b/riscv-tools index 6953e5c4..7219be43 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 6953e5c4a32afd0055200578a3e7eda064f58859 +Subproject commit 7219be435a89277603e566e806ae8540c7f9a917 diff --git a/rocket b/rocket index 5c6f470e..94e2174a 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 5c6f470ef4b5eba3a654b37a0b1767a25a5be437 +Subproject commit 94e2174ab654e0458a2d7cdc02980a0991299c9f diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index f0447161..6d7e29fa 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -169,11 +169,11 @@ class BaseConfig extends Config ( //Tile Constants case BuildTiles => { val (rvi, rvu) = - if (site(XLen) == 64) (rv64i, rv64u) - else (rv32i, rv32u) + if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u) + else ((if (site(UseVM)) rv32i else rv32pi), rv32u) TestGeneration.addSuites(rvi.map(_("p"))) TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks) List.fill(site(NTiles)){ (r: Bool, p: Parameters) => Module(new RocketTile(resetSignal = r)(p.alterPartial({ case TLId => "L1toL2" @@ -569,3 +569,7 @@ class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new De class DualCoreConfig extends Config( new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig) + +class TinyConfig extends Config( + new WithRV32 ++ new WithSmallCores ++ + new WithStatelessBridge ++ new BaseConfig) diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index 90f11b75..da01df99 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -105,14 +105,15 @@ object DefaultTestSuites { val rv32uaNames = LinkedHashSet("lrsc", "amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w") val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_) - val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi") + val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi", "dirty") val rv32si = new AssemblyTestSuite("rv32si", rv32siNames)(_) - val rv32miNames = LinkedHashSet("breakpoint", "csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall") + val rv32miNames = LinkedHashSet("csr", "mcsr", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall") val rv32mi = new AssemblyTestSuite("rv32mi", rv32miNames)(_) val rv32u = List(rv32ui, rv32um) val rv32i = List(rv32ui, rv32si, rv32mi) + val rv32pi = List(rv32ui, rv32mi) val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw") val rv64ui = new AssemblyTestSuite("rv64ui", rv32uiNames ++ rv64uiNames)(_) @@ -134,7 +135,7 @@ object DefaultTestSuites { val rv64siNames = rv32siNames val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_) - val rv64miNames = rv32miNames + val rv64miNames = rv32miNames + "breakpoint" val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_) val groundtestNames = LinkedHashSet("simple") @@ -145,6 +146,7 @@ object DefaultTestSuites { val rv64u = List(rv64ui, rv64um) val rv64i = List(rv64ui, rv64si, rv64mi) + val rv64pi = List(rv64ui, rv64mi) val benchmarks = new BenchmarkTestSuite("basic", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet( "median", "multiply", "qsort", "towers", "vvadd", "dhrystone", "mt-matmul"))