riscv/rocket-chip
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fix assembly tests for configurations without VMU and/or user mode

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This commit is contained in:
Howard Mao
2016-07-22 11:36:45 -07:00
parent 75347eed56
commit 6a5b2d7f59
5 changed files with 15 additions and 9 deletions
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10
src/main/scala/Configs.scala
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@ -169,11 +169,11 @@ class BaseConfig extends Config (
//Tile Constants
case BuildTiles => {
val (rvi, rvu) =
if (site(XLen) == 64) (rv64i, rv64u)
else (rv32i, rv32u)
if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)
List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
Module(new RocketTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
@ -569,3 +569,7 @@ class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new De
class DualCoreConfig extends Config(
new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
class TinyConfig extends Config(
new WithRV32 ++ new WithSmallCores ++
new WithStatelessBridge ++ new BaseConfig)