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fix up SmiMem

This commit is contained in:
Howard Mao 2016-01-14 16:41:22 -08:00
parent 335fb73120
commit 6a0352c6d0

View File

@ -35,7 +35,7 @@ class SmiMem(val dataWidth: Int, val memDepth: Int) extends SmiPeripheral {
// override
val addrWidth = log2Up(memDepth)
val mem = SeqMem(Bits(width = dataWidth), memDepth)
val mem = SeqMem(memDepth, Bits(width = dataWidth))
val ren = io.req.fire() && !io.req.bits.rw
val wen = io.req.fire() && io.req.bits.rw