Merge remote-tracking branch 'origin/master' into periphery-adjustments

src/main/scala/uncore/tilelink2/SRAM.scala

@@ -5,6 +5,7 @@ package uncore.tilelink2
 import Chisel._
 import config._
 import diplomacy._
+import util._
 
 class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
 {
@@ -73,7 +74,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
       mem.write(memAddress, wdata, in.a.bits.mask.toBools)
     }
     val ren = in.a.fire() && read
-    rdata := holdUnless(mem.read(memAddress, ren), RegNext(ren))
+    rdata := mem.readAndHold(memAddress, ren)
 
     // Tie off unused channels
     in.b.valid := Bool(false)

src/main/scala/uncore/tilelink2/SourceShrinker.scala

@@ -6,6 +6,7 @@ import Chisel._
 import chisel3.internal.sourceinfo.SourceInfo
 import config._
 import diplomacy._
+import util._
 import scala.math.{min,max}
 
 class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyModule
@@ -54,7 +55,7 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
         in.a.ready := out.a.ready && !block
         out.a.valid := in.a.valid && !block
         out.a.bits := in.a.bits
-        out.a.bits.source := holdUnless(nextFree, a_first)
+        out.a.bits.source := nextFree holdUnless a_first
 
         in.d <> out.d
         in.d.bits.source := sourceIdMap(out.d.bits.source)

src/main/scala/uncore/tilelink2/package.scala

@@ -4,6 +4,7 @@ package uncore
 
 import Chisel._
 import diplomacy._
+import util._
 
 package object tilelink2
 {
@@ -16,7 +17,6 @@ package object tilelink2
   def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
   def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))
   def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
-  def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
   def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
   // Fill 1s from low bits to high bits
   def leftOR(x: UInt) = {