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coreplex: better names for RocketTiles in Verilog (#890)

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This commit is contained in:
Yunsup Lee
2017-07-25 16:35:31 -07:00
committed by GitHub
parent d43f02268b
commit 6916e5cbfb
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/coreplex/RocketCoreplex.scala
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@@ -35,7 +35,7 @@ trait HasRocketTiles extends HasSystemBus
// Make a wrapper for each tile that will wire it to coreplex devices and crossbars, // Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
// according to the specified type of clock crossing. // according to the specified type of clock crossing.
val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex
val wrappers: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, c), i) => val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, c), i) =>
val pWithExtra = p.alterPartial { val pWithExtra = p.alterPartial {
case TileKey => c case TileKey => c
case BuildRoCC => c.rocc case BuildRoCC => c.rocc
@@ -105,7 +105,7 @@ trait HasRocketTilesModuleImp extends LazyMultiIOModuleImp
val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs)) val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs))
// Unconditionally wire up the non-diplomatic tile inputs // Unconditionally wire up the non-diplomatic tile inputs
outer.wrappers.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) => outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
tile.clock := wire.clock tile.clock := wire.clock
tile.reset := wire.reset tile.reset := wire.reset
tile.io.hartid := wire.hartid tile.io.hartid := wire.hartid