riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

chiplink: adjust bus view to include the splitter (#886)

Browse Source
This commit is contained in:
Wesley W. Terpstra authored and GitHub committed 2017-07-24 21:41:17 -07:00
1 parent dc435af30a
commit 68ed055f6d
3 files changed
+9 -4
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/tilelink/Bus.scala
-2
View File
@@ -45,8 +45,6 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
protected def inwardNode: TLInwardNode = xbar.node
protected def inwardBufNode: TLInwardNode = master_buffer.node
def edgesIn = xbar.node.edgesIn
def bufferFromMasters: TLInwardNode = inwardBufNode
def bufferToSlaves: TLOutwardNode = outwardBufNode