diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 954d6200..bd87dea6 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -20,6 +20,7 @@ case object SystemBusParams extends Field[SystemBusParams]
 class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
   private val master_splitter = LazyModule(new TLSplitter)  // Allows cycle-free connection to external networks
   inwardBufNode :=* master_splitter.node
+  def busView = master_splitter.node.edgesIn.head
 
   protected def inwardSplitNode: TLInwardNode = master_splitter.node
   protected def outwardSplitNode: TLOutwardNode = master_splitter.node
@@ -41,6 +42,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     sink.node
   }
 
+  def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = {
+    val buffer = LazyModule(new TLBuffer(params))
+    inwardNode :=* buffer.node
+    buffer.node
+  }
+
   def fromSyncTiles(params: BufferParams): TLInwardNode = {
     val buf = LazyModule(new TLBuffer(params))
     tile_fixer.node :=* buf.node
@@ -93,5 +100,5 @@ trait HasSystemBus extends HasInterruptBus {
 
   val sbus = new SystemBus(sbusParams)
 
-  def sharedMemoryTLEdge: TLEdge = sbus.edgesIn.head
+  def sharedMemoryTLEdge: TLEdge = sbus.busView
 }
diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala
index fc58912a..63730436 100644
--- a/src/main/scala/groundtest/Coreplex.scala
+++ b/src/main/scala/groundtest/Coreplex.scala
@@ -21,7 +21,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
   val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
     c.build(i, p.alterPartial {
       case TileKey => c
-      case SharedMemoryTLEdge => sbus.edgesIn.head
+      case SharedMemoryTLEdge => sbus.busView
     })
   )}
 
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index 3795be10..134a14f7 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -45,8 +45,6 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
   protected def inwardNode: TLInwardNode = xbar.node
   protected def inwardBufNode: TLInwardNode = master_buffer.node
 
-  def edgesIn = xbar.node.edgesIn
-
   def bufferFromMasters: TLInwardNode = inwardBufNode
 
   def bufferToSlaves: TLOutwardNode = outwardBufNode