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chiplink: adjust bus view to include the splitter (#886)

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This commit is contained in:
Wesley W. Terpstra
2017-07-24 21:41:17 -07:00
committed by GitHub
parent dc435af30a
commit 68ed055f6d
3 changed files with 9 additions and 4 deletions
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9
src/main/scala/coreplex/SystemBus.scala
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@ -20,6 +20,7 @@ case object SystemBusParams extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
inwardBufNode :=* master_splitter.node
def busView = master_splitter.node.edgesIn.head
protected def inwardSplitNode: TLInwardNode = master_splitter.node
protected def outwardSplitNode: TLOutwardNode = master_splitter.node
@ -41,6 +42,12 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
sink.node
}
def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = {
val buffer = LazyModule(new TLBuffer(params))
inwardNode :=* buffer.node
buffer.node
}
def fromSyncTiles(params: BufferParams): TLInwardNode = {
val buf = LazyModule(new TLBuffer(params))
tile_fixer.node :=* buf.node
@ -93,5 +100,5 @@ trait HasSystemBus extends HasInterruptBus {
val sbus = new SystemBus(sbusParams)
def sharedMemoryTLEdge: TLEdge = sbus.edgesIn.head
def sharedMemoryTLEdge: TLEdge = sbus.busView
}