riscv/rocket-chip
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refactor tilelink params

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This commit is contained in:
Henry Cook 2015-10-13 23:42:53 -07:00
parent 4508666d96
commit 68cb54bc68
2 changed files with 9 additions and 7 deletions
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5
rocket/src/main/scala/icache.scala
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@ -5,8 +5,9 @@ import uncore._
import Util._ import Util._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters { trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLDataBeats) val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLDataBits) val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val outerAddrBits = p(TLKey(p(TLId))).addrBits
val refillCyclesPerBeat = outerDataBits/rowBits val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats val refillCycles = refillCyclesPerBeat*outerDataBeats
} }

11
rocket/src/main/scala/nbdcache.scala
View File

@ -18,7 +18,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
val wordBits = p(WordBits) val wordBits = p(WordBits)
val wordBytes = wordBits/8 val wordBytes = wordBits/8
val wordOffBits = log2Up(wordBytes) val wordOffBits = log2Up(wordBytes)
val beatBytes = p(CacheBlockBytes) / p(TLDataBeats) val beatBytes = p(CacheBlockBytes) / outerDataBeats
val beatWords = beatBytes / wordBytes val beatWords = beatBytes / wordBytes
val beatOffBits = log2Up(beatBytes) val beatOffBits = log2Up(beatBytes)
val idxMSB = untagBits-1 val idxMSB = untagBits-1
@ -32,6 +32,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
val sdqDepth = p(StoreDataQueueDepth) val sdqDepth = p(StoreDataQueueDepth)
val nMSHRs = p(NMSHRs) val nMSHRs = p(NMSHRs)
val nIOMSHRs = p(NIOMSHRs) val nIOMSHRs = p(NIOMSHRs)
val lrscCycles = p(LRSCCycles)
} }
abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
@ -713,11 +714,11 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val mem = new ClientTileLinkIO val mem = new ClientTileLinkIO
} }
require(p(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed require(lrscCycles >= 32) // ISA requires 16-insn LRSC sequences to succeed
require(isPow2(nSets)) require(isPow2(nSets))
require(isPow2(nWays)) // TODO: relax this require(isPow2(nWays)) // TODO: relax this
require(p(RowBits) <= p(TLDataBits)) require(rowBits <= outerDataBits)
require(paddrBits-blockOffBits == p(TLBlockAddrBits) ) require(paddrBits-blockOffBits == outerAddrBits)
require(untagBits <= pgIdxBits) require(untagBits <= pgIdxBits)
val wb = Module(new WritebackUnit) val wb = Module(new WritebackUnit)
@ -861,7 +862,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
when (lrsc_valid) { lrsc_count := lrsc_count - 1 } when (lrsc_valid) { lrsc_count := lrsc_count - 1 }
when (s2_valid_masked && s2_hit || s2_replay) { when (s2_valid_masked && s2_hit || s2_replay) {
when (s2_lr) { when (s2_lr) {
when (!lrsc_valid) { lrsc_count := p(LRSCCycles)-1 } when (!lrsc_valid) { lrsc_count := lrscCycles-1 }
lrsc_addr := s2_req.addr >> blockOffBits lrsc_addr := s2_req.addr >> blockOffBits
} }
when (s2_sc) { when (s2_sc) {