From 68cb54bc6818482cb4982f0e0426accac31da1f3 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 13 Oct 2015 23:42:53 -0700
Subject: [PATCH] refactor tilelink params

---
 rocket/src/main/scala/icache.scala   |  5 +++--
 rocket/src/main/scala/nbdcache.scala | 11 ++++++-----
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index b7f2c565..de3c1fd4 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -5,8 +5,9 @@ import uncore._
 import Util._
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
-  val outerDataBeats = p(TLDataBeats)
-  val outerDataBits = p(TLDataBits)
+  val outerDataBeats = p(TLKey(p(TLId))).dataBeats
+  val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
+  val outerAddrBits = p(TLKey(p(TLId))).addrBits
   val refillCyclesPerBeat = outerDataBits/rowBits
   val refillCycles = refillCyclesPerBeat*outerDataBeats
 }
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index d71cbf8f..111accef 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -18,7 +18,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
   val wordBits = p(WordBits)
   val wordBytes = wordBits/8
   val wordOffBits = log2Up(wordBytes)
-  val beatBytes = p(CacheBlockBytes) / p(TLDataBeats)
+  val beatBytes = p(CacheBlockBytes) / outerDataBeats
   val beatWords = beatBytes / wordBytes
   val beatOffBits = log2Up(beatBytes)
   val idxMSB = untagBits-1
@@ -32,6 +32,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
   val sdqDepth = p(StoreDataQueueDepth)
   val nMSHRs = p(NMSHRs)
   val nIOMSHRs = p(NIOMSHRs)
+  val lrscCycles = p(LRSCCycles)
 }
 
 abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
@@ -713,11 +714,11 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     val mem = new ClientTileLinkIO
   }
  
-  require(p(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
+  require(lrscCycles >= 32) // ISA requires 16-insn LRSC sequences to succeed
   require(isPow2(nSets))
   require(isPow2(nWays)) // TODO: relax this
-  require(p(RowBits) <= p(TLDataBits))
-  require(paddrBits-blockOffBits == p(TLBlockAddrBits) )
+  require(rowBits <= outerDataBits)
+  require(paddrBits-blockOffBits == outerAddrBits)
   require(untagBits <= pgIdxBits)
 
   val wb = Module(new WritebackUnit)
@@ -861,7 +862,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   when (lrsc_valid) { lrsc_count := lrsc_count - 1 }
   when (s2_valid_masked && s2_hit || s2_replay) {
     when (s2_lr) {
-      when (!lrsc_valid) { lrsc_count := p(LRSCCycles)-1 }
+      when (!lrsc_valid) { lrsc_count := lrscCycles-1 }
       lrsc_addr := s2_req.addr >> blockOffBits
     }
     when (s2_sc) {