riscv/rocket-chip
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refactor tilelink params

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Henry Cook committed 2015-10-14 12:14:36 -07:00
1 parent 4508666d96
commit 68cb54bc68
2 files changed
+9 -7
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rocket/src/main/scala/icache.scala
+3 -2
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@@ -5,8 +5,9 @@ import uncore._
import Util._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLDataBeats)
val outerDataBits = p(TLDataBits)
val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val outerAddrBits = p(TLKey(p(TLId))).addrBits
val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}