riscv/rocket-chip
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refactor tilelink params

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This commit is contained in:
Henry Cook
2015-10-13 23:42:53 -07:00
parent 4508666d96
commit 68cb54bc68
2 changed files with 9 additions and 7 deletions
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5
rocket/src/main/scala/icache.scala
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@ -5,8 +5,9 @@ import uncore._
import Util._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLDataBeats)
val outerDataBits = p(TLDataBits)
val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val outerAddrBits = p(TLKey(p(TLId))).addrBits
val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}