riscv/rocket-chip
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Default RowBits to TileLink width, not XLen

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Andrew Waterman 2016-04-01 16:40:30 -07:00 committed by Henry Cook
parent 46d7dceb1e
commit 6878e3265f
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/Configs.scala
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@ -105,7 +105,7 @@ class DefaultConfig extends Config (
case "L1I" => { case "L1I" => {
case NSets => Knob("L1I_SETS") //64 case NSets => Knob("L1I_SETS") //64
case NWays => Knob("L1I_WAYS") //4 case NWays => Knob("L1I_WAYS") //4
case RowBits => 4*site(CoreInstBits) case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
case NTLBEntries => 8 case NTLBEntries => 8
case CacheIdBits => 0 case CacheIdBits => 0
case SplitMetadata => false case SplitMetadata => false
@ -113,7 +113,7 @@ class DefaultConfig extends Config (
case "L1D" => { case "L1D" => {
case NSets => Knob("L1D_SETS") //64 case NSets => Knob("L1D_SETS") //64
case NWays => Knob("L1D_WAYS") //4 case NWays => Knob("L1D_WAYS") //4
case RowBits => 2*site(CoreDataBits) case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
case NTLBEntries => 8 case NTLBEntries => 8
case CacheIdBits => 0 case CacheIdBits => 0
case SplitMetadata => false case SplitMetadata => false