riscv/rocket-chip
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refactor ICache to be reusable by other frontends (#808)

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* refactor ICache to be reusable by other frontends

specifically one that would like to change the fetch width and number of
bytes in an instruction
This commit is contained in:
Colin Schmidt
2017-06-20 08:21:01 -07:00
committed by GitHub
parent ff1f0170dc
commit 675f183dd2
2 changed files with 14 additions and 12 deletions
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7
src/main/scala/rocket/Frontend.scala
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@ -45,9 +45,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val perf = new FrontendPerfEvents().asInput
}
class Frontend(hartid: Int)(implicit p: Parameters) extends LazyModule {
class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(latency = 2, hartid))
val icache = LazyModule(new ICache(icacheParams, hartid))
val masterNode = TLOutputNode()
val slaveNode = TLInputNode()
@ -70,6 +70,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val io = new FrontendBundle(outer)
implicit val edge = outer.masterNode.edgesOut.head
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries))
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 4, flow = true)) }
@ -183,7 +184,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(hartid: Int))
val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
val hartid: Int
tileBus.node := frontend.masterNode
nPTWPorts += 1