riscv/rocket-chip
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Fixed BHT update error.

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- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
This commit is contained in:
Christopher Celio
2014-11-16 22:02:27 -08:00
parent fea31d2167
commit 6749f67b7f
4 changed files with 54 additions and 40 deletions
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4
rocket/src/main/scala/icache.scala
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@ -33,6 +33,7 @@ class CPUFrontendIO extends CoreBundle {
val resp = Decoupled(new FrontendResp).flip
val btb_resp = Valid(new BTBResp).flip
val btb_update = Valid(new BTBUpdate)
val bht_update = Valid(new BHTUpdate)
val ras_update = Valid(new RASUpdate)
val ptw = new TLBPTWIO().flip
val invalidate = Bool(OUTPUT)
@ -88,7 +89,8 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
btb.io.req.valid := !stall && !icmiss
btb.io.req.bits.addr := s1_pc & SInt(-coreInstBytes)
btb.io.update := io.cpu.btb_update
btb.io.btb_update := io.cpu.btb_update
btb.io.bht_update := io.cpu.bht_update
btb.io.ras_update := io.cpu.ras_update
btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate