riscv/rocket-chip
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make sure CSR width is parameterizable

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This commit is contained in:
Howard Mao 2016-01-28 14:06:38 -08:00
parent adaec18bec
commit 66e9cc8c82
3 changed files with 17 additions and 13 deletions
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10
uncore/src/main/scala/dma.scala
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@ -19,8 +19,6 @@ trait HasDmaParameters {
val addrBits = p(PAddrBits) val addrBits = p(PAddrBits)
val dmaStatusBits = 2 val dmaStatusBits = 2
val dmaWordSizeBits = 2 val dmaWordSizeBits = 2
val csrDataBits = 64
val csrDataBytes = csrDataBits / 8
} }
abstract class DmaModule(implicit val p: Parameters) extends Module with HasDmaParameters abstract class DmaModule(implicit val p: Parameters) extends Module with HasDmaParameters
@ -82,8 +80,12 @@ class DmaTrackerIO(implicit p: Parameters) extends DmaBundle()(p) {
val mmio = new NastiIO val mmio = new NastiIO
} }
class DmaManager(outstandingCSR: Int)(implicit p: Parameters) extends DmaModule()(p) class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
with HasNastiParameters with HasAddrMapParameters { extends DmaModule()(p)
with HasNastiParameters
with HasAddrMapParameters
with HasHtifParameters {
val io = new Bundle { val io = new Bundle {
val ctrl = (new NastiIO).flip val ctrl = (new NastiIO).flip
val mmio = new NastiIO val mmio = new NastiIO

16
uncore/src/main/scala/htif.scala
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@ -9,20 +9,22 @@ import cde.{Parameters, Field}
case object HtifKey extends Field[HtifParameters] case object HtifKey extends Field[HtifParameters]
case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, nSCR: Int = 64) case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, csrDataBits: Int, nSCR: Int = 64)
trait HasHtifParameters { trait HasHtifParameters {
implicit val p: Parameters implicit val p: Parameters
val external = p(HtifKey) val htifExternal = p(HtifKey)
val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val dataBeats = p(TLKey(p(TLId))).dataBeats val dataBeats = p(TLKey(p(TLId))).dataBeats
val w = external.width val w = htifExternal.width
val nSCR = external.nSCR val nSCR = htifExternal.nSCR
val scrAddrBits = log2Up(nSCR) val scrAddrBits = log2Up(nSCR)
val scrDataBits = 64 val scrDataBits = 64
val scrDataBytes = scrDataBits / 8 val scrDataBytes = scrDataBits / 8
val offsetBits = external.offsetBits val csrDataBits = htifExternal.csrDataBits
val nCores = external.nCores val csrDataBytes = csrDataBits / 8
val offsetBits = htifExternal.offsetBits
val nCores = htifExternal.nCores
} }
abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters
@ -40,7 +42,7 @@ class HostIO(w: Int) extends Bundle {
class HtifIO(implicit p: Parameters) extends HtifBundle()(p) { class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores)) val id = UInt(INPUT, log2Up(nCores))
val csr = new SmiIO(scrDataBits, 12).flip val csr = new SmiIO(csrDataBits, 12).flip
val debug_stats_csr = Bool(OUTPUT) val debug_stats_csr = Bool(OUTPUT)
// wired directly to stats register // wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work

4
uncore/src/main/scala/rtc.scala
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@ -11,7 +11,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
val io = new NastiIO val io = new NastiIO
val addrTable = Vec.tabulate(nCores) { i => val addrTable = Vec.tabulate(nCores) { i =>
UInt(addrMap(s"conf:csr$i").start + csr_MTIME * scrDataBytes) UInt(addrMap(s"conf:csr$i").start + csr_MTIME * csrDataBytes)
} }
val rtc = Reg(init=UInt(0, scrDataBits)) val rtc = Reg(init=UInt(0, scrDataBits))
@ -50,7 +50,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
io.aw.bits := NastiWriteAddressChannel( io.aw.bits := NastiWriteAddressChannel(
id = coreId, id = coreId,
addr = addrTable(coreId), addr = addrTable(coreId),
size = UInt(log2Up(scrDataBytes))) size = UInt(log2Up(csrDataBytes)))
io.w.valid := sending_data io.w.valid := sending_data
io.w.bits := NastiWriteDataChannel(data = rtc) io.w.bits := NastiWriteDataChannel(data = rtc)