diff --git a/uncore/src/main/scala/dma.scala b/uncore/src/main/scala/dma.scala
index 69a3fb26..16fa01b0 100644
--- a/uncore/src/main/scala/dma.scala
+++ b/uncore/src/main/scala/dma.scala
@@ -19,8 +19,6 @@ trait HasDmaParameters {
   val addrBits = p(PAddrBits)
   val dmaStatusBits = 2
   val dmaWordSizeBits = 2
-  val csrDataBits = 64
-  val csrDataBytes = csrDataBits / 8
 }
 
 abstract class DmaModule(implicit val p: Parameters) extends Module with HasDmaParameters
@@ -82,8 +80,12 @@ class DmaTrackerIO(implicit p: Parameters) extends DmaBundle()(p) {
   val mmio = new NastiIO
 }
 
-class DmaManager(outstandingCSR: Int)(implicit p: Parameters) extends DmaModule()(p)
-    with HasNastiParameters with HasAddrMapParameters {
+class DmaManager(outstandingCSR: Int)(implicit p: Parameters)
+    extends DmaModule()(p)
+    with HasNastiParameters
+    with HasAddrMapParameters
+    with HasHtifParameters {
+
   val io = new Bundle {
     val ctrl = (new NastiIO).flip
     val mmio = new NastiIO
diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala
index 9b72459b..f20d1954 100644
--- a/uncore/src/main/scala/htif.scala
+++ b/uncore/src/main/scala/htif.scala
@@ -9,20 +9,22 @@ import cde.{Parameters, Field}
 
 case object HtifKey extends Field[HtifParameters]
 
-case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, nSCR: Int = 64)
+case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, csrDataBits: Int, nSCR: Int = 64)
 
 trait HasHtifParameters {
   implicit val p: Parameters
-  val external = p(HtifKey)
+  val htifExternal = p(HtifKey)
   val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
   val dataBeats = p(TLKey(p(TLId))).dataBeats
-  val w = external.width
-  val nSCR = external.nSCR
+  val w = htifExternal.width
+  val nSCR = htifExternal.nSCR
   val scrAddrBits = log2Up(nSCR)
   val scrDataBits = 64
   val scrDataBytes = scrDataBits / 8
-  val offsetBits = external.offsetBits
-  val nCores = external.nCores
+  val csrDataBits = htifExternal.csrDataBits
+  val csrDataBytes = csrDataBits / 8
+  val offsetBits = htifExternal.offsetBits
+  val nCores = htifExternal.nCores
 }
 
 abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters
@@ -40,7 +42,7 @@ class HostIO(w: Int) extends Bundle {
 class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
   val reset = Bool(INPUT)
   val id = UInt(INPUT, log2Up(nCores))
-  val csr = new SmiIO(scrDataBits, 12).flip
+  val csr = new SmiIO(csrDataBits, 12).flip
   val debug_stats_csr = Bool(OUTPUT)
     // wired directly to stats register
     // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
diff --git a/uncore/src/main/scala/rtc.scala b/uncore/src/main/scala/rtc.scala
index 830c4351..6c3f83a4 100644
--- a/uncore/src/main/scala/rtc.scala
+++ b/uncore/src/main/scala/rtc.scala
@@ -11,7 +11,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
   val io = new NastiIO
 
   val addrTable = Vec.tabulate(nCores) { i =>
-    UInt(addrMap(s"conf:csr$i").start + csr_MTIME * scrDataBytes)
+    UInt(addrMap(s"conf:csr$i").start + csr_MTIME * csrDataBytes)
   }
 
   val rtc = Reg(init=UInt(0, scrDataBits))
@@ -50,7 +50,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
   io.aw.bits := NastiWriteAddressChannel(
     id = coreId,
     addr = addrTable(coreId),
-    size = UInt(log2Up(scrDataBytes)))
+    size = UInt(log2Up(csrDataBytes)))
 
   io.w.valid := sending_data
   io.w.bits := NastiWriteDataChannel(data = rtc)