riscv/rocket-chip
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rocket: TIMs should never be cached

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This commit is contained in:
Henry Cook 2017-10-11 18:22:52 -07:00
parent b64609bfe8
commit 66e4bfc2d9
4 changed files with 6 additions and 5 deletions
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4
src/main/scala/groundtest/Coreplex.scala
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@ -29,7 +29,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
sbus.fromSyncTiles(BufferParams.default, TileMasterPortParams().adapterChain(this)) :=* _.node
}
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))
pbusRAM.node := pbus.toVariableWidthSlaves
override lazy val module = new GroundTestCoreplexModule(this)
@ -47,7 +47,7 @@ class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends Base
/** Adds a SRAM to the system for testing purposes. */
trait HasPeripheryTestRAMSlave extends HasPeripheryBus {
val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, pbus.beatBytes))
val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, true, pbus.beatBytes))
testram.node := pbus.toVariableWidthSlaves
}

2
src/main/scala/rocket/ICache.scala
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@ -59,7 +59,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
regionType = RegionType.UNCACHEABLE,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),
supportsPutPartial = TransferSizes(1, wordBytes),

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -18,7 +18,7 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
Seq(TLManagerParameters(
address = List(address),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
regionType = RegionType.UNCACHEABLE,
executable = true,
supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
supportsLogical = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,

3
src/main/scala/tilelink/SRAM.scala
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@ -10,6 +10,7 @@ import freechips.rocketchip.util._
class TLRAM(
address: AddressSet,
cacheable: Boolean = true,
executable: Boolean = true,
beatBytes: Int = 4,
devName: Option[String] = None,
@ -20,7 +21,7 @@ class TLRAM(
Seq(TLManagerParameters(
address = List(address) ++ errors,
resources = resources,
regionType = RegionType.UNCACHED,
regionType = if (cacheable) RegionType.UNCACHED else RegionType.UNCACHEABLE,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),