From 66e4bfc2d9aa9a8eaf9df2f912d24524fdc34e43 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 11 Oct 2017 18:22:52 -0700 Subject: [PATCH] rocket: TIMs should never be cached --- src/main/scala/groundtest/Coreplex.scala | 4 ++-- src/main/scala/rocket/ICache.scala | 2 +- src/main/scala/rocket/ScratchpadSlavePort.scala | 2 +- src/main/scala/tilelink/SRAM.scala | 3 ++- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index b9ee65cf..ee8ebe6b 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -29,7 +29,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex sbus.fromSyncTiles(BufferParams.default, TileMasterPortParams().adapterChain(this)) :=* _.node } - val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes)) + val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes)) pbusRAM.node := pbus.toVariableWidthSlaves override lazy val module = new GroundTestCoreplexModule(this) @@ -47,7 +47,7 @@ class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends Base /** Adds a SRAM to the system for testing purposes. */ trait HasPeripheryTestRAMSlave extends HasPeripheryBus { - val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, pbus.beatBytes)) + val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, true, pbus.beatBytes)) testram.node := pbus.toVariableWidthSlaves } diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index bfaeec4d..b2d90f1e 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -59,7 +59,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame Seq(TLManagerParameters( address = Seq(AddressSet(itimAddr, size-1)), resources = device.reg("mem"), - regionType = RegionType.UNCACHED, + regionType = RegionType.UNCACHEABLE, executable = true, supportsPutFull = TransferSizes(1, wordBytes), supportsPutPartial = TransferSizes(1, wordBytes), diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 5f769962..dd8d002b 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -18,7 +18,7 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics: Seq(TLManagerParameters( address = List(address), resources = device.reg("mem"), - regionType = RegionType.UNCACHED, + regionType = RegionType.UNCACHEABLE, executable = true, supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none, supportsLogical = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none, diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index 08cc0b1e..9f77903a 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -10,6 +10,7 @@ import freechips.rocketchip.util._ class TLRAM( address: AddressSet, + cacheable: Boolean = true, executable: Boolean = true, beatBytes: Int = 4, devName: Option[String] = None, @@ -20,7 +21,7 @@ class TLRAM( Seq(TLManagerParameters( address = List(address) ++ errors, resources = resources, - regionType = RegionType.UNCACHED, + regionType = if (cacheable) RegionType.UNCACHED else RegionType.UNCACHEABLE, executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes),