riscv/rocket-chip
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rocket: TIMs should never be cached

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This commit is contained in:
Henry Cook
2017-10-11 18:22:52 -07:00
parent b64609bfe8
commit 66e4bfc2d9
4 changed files with 6 additions and 5 deletions
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3
src/main/scala/tilelink/SRAM.scala
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@ -10,6 +10,7 @@ import freechips.rocketchip.util._
class TLRAM(
address: AddressSet,
cacheable: Boolean = true,
executable: Boolean = true,
beatBytes: Int = 4,
devName: Option[String] = None,
@ -20,7 +21,7 @@ class TLRAM(
Seq(TLManagerParameters(
address = List(address) ++ errors,
resources = resources,
regionType = RegionType.UNCACHED,
regionType = if (cacheable) RegionType.UNCACHED else RegionType.UNCACHEABLE,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),